適用於DE2-70
module Priority_en(SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 );
input [17:0] SW; // toggle switches
input [7:0] KEY; // Push bottom
input CLOCK_27; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [7:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
//set original program input , output
// y, sel, a, b, c);
//output [3:0] y;
//input [2:0] sel;
//input [3:0] a, b, c;
reg [3:0] y ;
wire [2:0] sel;
wire [3:0] a,b,c;
wire [7:0] segout;
//mapping to hardware
assign LEDR = SW;
assign sel=SW[17:15];
assign a=SW[3:0];
assign b=SW[7:4];
assign c=SW[11:8];
always @ (sel or a or b or c)
begin
casez (sel)
3'bzz1 : y=a;
3'bz10 : y=b;
3'b100 : y=c;
default : y=4'bzzzz;
endcase
end
assign LEDG[3:0]=y;
//module _7seg(hex , seg);
_7seg UUT1(.hex(y),
.seg(segout));
assign HEX0=segout[6:0];
endmodule
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
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