使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計Traffic Lights為例(FPGA開發平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計Traffic Lights為例(FPGA開發平台) 

Traffic Lights

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );
 input  [17:0] SW;   // toggle switches
 input  [7:0] KEY;       // Push bottom
 input  CLOCK_50;   //Clock 27MHz , 50Mhz
 output [17:0] LEDR;   // red  LEDS
 output [8:0] LEDG;   // green LEDs
 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
 output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
 inout  [35:0] GPIO;
 assign HEX0=7'b111_1111;
 assign HEX1=7'b111_1111;
 assign HEX2=7'b111_1111;
 assign HEX3=7'b111_1111;
 assign HEX4=7'b111_1111;
 assign HEX5=7'b111_1111;
 assign HEX6=7'b111_1111;
 assign HEX7=7'b111_1111;
 
 wire oClk_1MHz,oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1 ;
 MHz50_1MHz u1 (CLOCK_50,KEY[0],oClk_1MHz);
 clk_1Hz u2  (oClk_1MHz,KEY[0],oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1);
 assign LEDR[17] = oClk1;
 
//module traffic_lights(M, R, Y, G, Button, CLK, RESETn);
//   output M;          // Green Man output light.
//   output R;          // Red traffic signal light.
//   output Y;          // Yellow (Amber) traffic signal light.
//   output G;          // Green traffic signal light.
//   input  Button;     // Pedestrian push button.
//   input  CLK;        // System clock.
//   input  RESETn;     // System reset.
   
 traffic_lights( LEDR[0],LEDR[1],LEDR[2],LEDR[3],KEY[0],oClk1,KEY[1]);
endmodule  

module MHz50_1MHz(Clk_in , Clr , Clk_out);  //除50
input  Clk_in , Clr;  // 一位元輸入
output reg Clk_out;
reg [4:0] cnt=5'b0_0000;
// counter size calculation according to input and output frequencies
parameter sys_clk = 50000000;  // 50 MHz system clock
parameter clkout = 1000000;  // 1 MHz clock output
parameter max = sys_clk / (2*clkout); // max-counter size
always@(posedge Clk_in or negedge Clr ) begin
  if (~Clr)
     begin
  cnt <= 0;
     end
  else if (cnt == max-1 )
     begin
  cnt <= 0;
  Clk_out <= ~Clk_out;
     end
  else
     begin
  cnt <= cnt + 1'd1;
     end
end
endmodule
// Ch10 clk_1Hz.v
// 由 10M Hz 除頻至 1 Hz
module clk_1Hz (Clk1M,Clr,Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1);
input  Clk1M,Clr;  // 一位元輸入
output Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1; // 一位元輸出
div10 D2 (Clk1M  , Clr, Clk100K);
div10 D3 (Clk100K, Clr, Clk10K );
div10 D4 (Clk10K , Clr, Clk1K  );
div10 D5 (Clk1K  , Clr, Clk100 );
div10 D6 (Clk100 , Clr, Clk10  );
div10 D7 (Clk10  , Clr, Clk1   );
endmodule
// Ch10 div10.v
// 除頻 /10
module div10 (Clk_i,Clr,Clk_o);
input  Clk_i,Clr; // 一位元輸入
output Clk_o;  // 一位元輸出
reg    Clk_o;  // 宣告為暫存器資料
reg    [3:0] Q;  // 宣告為暫存器資料
// MOD-10 (BCD) 除頻
always@ (posedge Clk_i or negedge Clr)
  if (~Clr )
 Q = 0;
  else if (Q == 9)
 Q = 0;
  else   
    Q = Q + 1;
// 形成對稱方波
always@ (Q)
  if (Q <= 4)  
 Clk_o  = 0;
  else          
 Clk_o  = 1;
endmodule 

//Traffic Lights
module traffic_lights(M, R, Y, G, Button, CLK, RESETn);
   output M;          // Green Man output light.
   output R;          // Red traffic signal light.
   output Y;          // Yellow (Amber) traffic signal light.
   output G;          // Green traffic signal light.
   input  Button;     // Pedestrian push button.
   input  CLK;        // System clock.
   input  RESETn;     // System reset.
   
   wire   S0;          // Current state least significant bit.
   wire   S1;
   wire   S2;          // Current state most significant bit.
   wire   S0n;         // Current state least significant bit.
   wire   S1n;
   wire   S2n;         // Current state most significant bit.
   wire   Next0;       // Next state least significant bit.
   wire   Next1;
   wire   Next2;       // Next state most significant bit.
   wire   ButtonReset; // Used to reset the push button SR flip-flop.
   wire   B;           // Output from the button state SR latch.
   wire   Bn;          // The complement of B.
   wire   w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13; // Linking wires.
   
   d_flip_flop_edge_triggered state0(S0, S0n, CLK, Next0);
   d_flip_flop_edge_triggered state1(S1, S1n, CLK, Next1);
   d_flip_flop_edge_triggered state2(S2, S2n, CLK, Next2);
   sr_latch_ungated button_state(B, Bn, Button, ButtonReset);
   
   // ButtonReset = !RESETn | M;
   not(RESET, RESETn);
   or(ButtonReset, RESET, M);
   
   // Next0 = !RESETn ? 1'b0 : (S1n & S2) | (S0 & S2) | (S0 & S1n) | (B & S1n & S2n);
   and(w1, S1n, S2);
   and(w2, S0, S2);
   and(w3, S0, S1n);
   and(w4, B, S1n, S2n);
   or(w5, w1, w2, w3, w4);
   and(Next0, RESETn, w5);
   
   // Next1 = !RESETn ? 1'b0 : (S0 & S2n) | (S1 & S2n);
   and(w6, S0, S2n);
   and(w7, S1, S2n);
   or(w8, w6,w7);
   and(Next1, RESETn, w8);
   
   // Next2 = !RESETn ? 1'b0 : S0n & S1 & S2n;    
   and(Next2, RESETn, S0n, S1, S2n);
   // M = not(S0) and S1 and not(S2)
   and(M, S0n, S1, S2n);
   // R = (not(S0) and S1) or (S1 and not(S2))
   and(w9, S0n, S1);
   and(w10, S1, S2n);
   or(R, w9, w10);
   // Y = (not(S1) and S2) or (S0 and S2) or (S0 and not(S1))
   and(w11, S1n, S2);
   and(w12, S0, S2);
   and(w13, S0, S1n);
   or(Y, w11, w12, w13);
   // G = not(S0) and not(S1) and not(S2)
   and(G, S0n, S1n, S2n);   
endmodule // traffic_lights_example
module d_flip_flop_edge_triggered(Q, Qn, C, D);
   output Q;
   output Qn;
   input  C;
   input  D;
   
   wire   Cn;   // Control input to the D latch.
   wire   Cnn;  // Control input to the SR latch.
   wire   DQ;   // Output from the D latch, inputs to the gated SR latch.
   wire   DQn;  // Output from the D latch, inputs to the gated SR latch.
   
   not(Cn, C);
   not(Cnn, Cn);   
   d_latch dl(DQ, DQn, Cn, D);
   sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);   
endmodule // d_flip_flop_edge_triggered
module d_latch(Q, Qn, G, D);
   output Q;
   output Qn;
   input  G;   
   input  D;
   wire   Dn; 
   wire   D1;
   wire   Dn1;
   
   not(Dn, D);   
   and(D1, G, D);
   and(Dn1, G, Dn);   
   nor(Qn, D1, Q);
   nor(Q, Dn1, Qn);
endmodule // d_latch
module sr_latch_gated(Q, Qn, G, S, R);
   output Q;
   output Qn;
   input  G;   
   input  S;
   input  R;
   
   wire   S1;
   wire   R1;
   
   and(S1, G, S);
   and(R1, G, R);   
   nor(Qn, S1, Q);
   nor(Q, R1, Qn);
endmodule // sr_latch_gated
module sr_latch_ungated(Q, Qn, S, R);
   output Q;
   output Qn;
   input  S;
   input  R;
   nor(Qn, S, Q);
   nor(Q, R, Qn);
endmodule // sr_latch_ungated