使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計 Counter Design using FSM 為例(FPGA開發平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計 Counter Design using FSM 為例(FPGA開發平台)

Counter Design using FSM

 Example :

3-bit Counter Design:

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );

 input  [17:0] SW;   // toggle switches

 input  [7:0] KEY;       // Push bottom

 input  CLOCK_50;   //Clock 27MHz , 50Mhz

 output [17:0] LEDR;   // red  LEDS

 output [8:0] LEDG;   // green LEDs

 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display

 output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display

 inout  [35:0] GPIO;

 assign HEX0=7'b111_1111;

 assign HEX1=7'b111_1111;

 assign HEX2=7'b111_1111;

 assign HEX3=7'b111_1111;

 assign HEX4=7'b111_1111;

 assign HEX5=7'b111_1111;

 assign HEX6=7'b111_1111;

 assign HEX7=7'b111_1111;

 

 wire clk1;

 //module Clock_1Hz(clk, reset, clk_1Hz);

 //input clk, reset;

 //output clk_1Hz;

 Clock_1Hz(CLOCK_50,KEY[0],clk1);

 

 //module BCDCount (CLK, clear, updn, a0, a1);

 //input CLK, reset, in;

 //output a0, a1;

 BCDCount (clk1, KEY[0], SW[0], LEDG[0], LEDG[1]);

 

endmodule

//1 HZ CLOCK GENERATOR

module Clock_1Hz(clk, reset, clk_1Hz);

input clk, reset;

output clk_1Hz;

reg clk_1Hz = 1'b0;

reg [27:0] counter;

always@(negedge reset or posedge clk)

begin

    if (!reset)

        begin

            clk_1Hz <= 0;

            counter <= 0;

        end

    else

        begin

            counter <= counter + 1;

            if ( counter == 25_000_000)

                begin

                    counter <= 0;

                    clk_1Hz <= ~clk_1Hz;

                end

        end

end

endmodule  

module BCDCount (CLK, clear, updn, a0, a1);

input CLK, clear, updn;

output a0, a1;

reg [1:0] state; // state variables

reg [1:0] next_state;

always @(posedge CLK) 

begin

state = next_state;

end

always @(state or clear or updn) 

begin

if (updn)

case (state)

2'b00: next_state = 2'b01;

2'b01: next_state = 2'b10;

2'b10: next_state = 2'b11;

2'b11: next_state = 2'b00;

endcase

else

case (state)

2'b00: next_state = 2'b11;

2'b01: next_state = 2'b00;

2'b10: next_state = 2'b01;

2'b11: next_state = 2'b10;

endcase

if (!clear) next_state = 2'b00;

end

assign  a0 = state[0];

assign  a1 = state[1];

endmodule