使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計Clock Divider 為例(FPGA開發平台)
module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );
input [17:0] SW; // toggle switches
input [7:0] KEY; // Push bottom
input CLOCK_50; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
inout [35:0] GPIO;
assign HEX0=7'b111_1111;
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;
/*module ClkDivider (
input clk,
input rst,
output reg clk_div
*/
ClkDivider(CLOCK_50 , SW[0] , LEDG[0]);
endmodule
module ClkDivider (
input clk,
input rst,
output reg clk_div );
parameter cNumber = 50000000; //25000000
reg [31:0] count;
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
count <= 32'b0;
else if (count == cNumber - 1)
count <= 32'b0;
else
count <= count + 1;
end
always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == cNumber - 1)
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end
endmodule
From : https://learn.digilentinc.com/Documents/262
In this example, we are going to use this clock divider to implement a signal of exactly 1 Hz frequency. First, we will need to calculate the constant. As an example, the input clock frequency of the Nexys3 is 100 MHz. We want our clk_div to be 1 Hz. So it should take 100000000 clock cycles before clk_div goes to '1' and returns to '0'. In another words, it takes 50000000 clock cycles for clk_div to flip its value. So the constant we need to choose here is 50000000. Now we will start to describe the circuit:
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