HBLbits_Verilog Basic
module top_module( input in, output out );
assign out=~in;
endmodule
endmodule
module top_module(
input a,
input b,
output out );
assign out=a&b;
endmodule
module top_module(
input a,
input b,
output out );
assign out=~(a|b);
endmodule
module top_module(
input a,
input b,
output out );
assign out=~(a ^ b);
endmodule
module top_module ( input in, // Declare an input wire named "in" output out // Declare an output wire named "out" ); wire not_in; // Declare a wire named "not_in" assign out = ~not_in; // Assign a value to out (create a NOT gate). assign not_in = ~in; // Assign a value to not_in (create another NOT gate). endmodule // End of module "top_module"
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire ab,cd;
assign ab=a&b;
assign cd=c&d;
assign out= ab | cd;
assign out_n=~out;
endmodule
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
wire abc1,def1,ab2,cd2;
assign abc1=p1a & p1b & p1c;
assign def1=p1d & p1e & p1f;
assign p1y=abc1 | def1;
assign ab2=p2a & p2b;
assign cd2=p2c & p2d;
assign p2y=ab2 | cd2;
endmodule
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