Verilog Circuits Sequential Logic ---- Sequential Logic Counters

 Counters

• Four-bit binary counter
• Decade counter
• Decade counter again
• Slow decade counter
• Counter 1-12
• Counter 1000
• 4-digit decimal counter
• 12-hour clock

Four-bit binary counter（Count15）

Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.

======================================

module top_module (

    input clk,

    input reset,      // Synchronous active-high reset

    output [3:0] q);

    always@ (posedge clk) begin

        if (reset)

            q=4'b0000;

        else

            q=q+1;

    end

 endmodule

Decade counter（Count10）

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.

======================================

module top_module (

    input clk,

    input reset,        // Synchronous active-high reset

    output [3:0] q);

    always@(posedge clk) begin

        if (reset)

            q=4'd0;

        else if(q==4'd9)

            q=4'd0;

        else

            q=q+1;

        

    end

endmodule

Decade counter again（Count1to10）

Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.

做一個十進制計數器，計數範圍為1到10（含1和10）。reset輸入是同步的，應將計數器覆位為1。

======================================

module top_module (

    input clk,

    input reset,

    output [3:0] q);

    always @(posedge clk ) begin

        if (reset)

            q=4'd1;

        else if (q==4'd10)

            q=4'd1;

        else

        q=q+1;

    end

endmodule

Slow decade counter（Countslow）

Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.

建立一個十進制計數器，該計數器的計數範圍為0到9（含0和9），周期為10。覆位輸入是同步的，應將計數器覆位為0。我們希望能夠暫停計數器，而不是總是在每個時鐘周期都遞增，因此，slowena輸入指示計數器應何時遞增。

======================================

module top_module (

    input clk,

    input slowena,

    input reset,

    output [3:0] q);

    always@(posedge clk)begin

        if(reset)

            q <= 'd0;

        else if(slowena)begin

            if(q=='d9)

                q <= 'd0;

            else

                q <= q + 1'b1;

        end

    end  

endmodule

Counter 1-12（Exams/ece241 2014 q7a）

Design a 1-12 counter with the following inputs and outputs:

• Reset Synchronous active-high reset that forces the counter to 1
• Enable Set high for the counter to run
• Clk Positive edge-triggered clock input
• Q[3:0] The output of the counter
• c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.

You have the following components available:

• the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
• logic gates

module count4(
	input clk,
	input enable,
	input load,
	input [3:0] d,
	output reg [3:0] Q
);

The c_enable, c_load, and c_d outputs are the signals that go to the internal counter's enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.

======================================

module top_module (

    input clk,

    input reset,

    input enable,

    output [3:0] Q,

    output c_enable,

    output c_load,

    output [3:0] c_d

); //

    

    assign c_enable = enable;

    assign c_load = reset | ((Q == 4'd12) && enable == 1'b1);

    assign c_d = c_load ? 4'd1 : 4'd0;

  // count4 the_counter (clk, c_enable, c_load, c_d /*, ... */ );

     count4 the_counter (

        .clk    (clk        ),

        .enable (c_enable   ),

        .load   (c_load     ),

        .d      (c_d        ),

        .Q      (Q          )

    );

endmodule

Counter 1000（Exams/ece241 2014 q7b）

From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).

The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.

module bcdcount (
	input clk,
	input reset,
	input enable,
	output reg [3:0] Q

);

======================================

module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //
  
	wire [3:0] q0, q1, q2;
    assign c_enable = {q1 == 4'd9 && q0 == 4'd9, q0 == 4'd9, 1'b1};
    assign OneHertz = {q2 == 4'd9 && q1 == 4'd9 && q0 == 4'd9};

	// bcdcount counter0 (clk, reset, c_enable[0]/*, ... */);
   	// bcdcount counter1 (clk, reset, c_enable[1]/*, ... */);   
    
    bcdcount counter0 (clk, reset, c_enable[0], q0);
    bcdcount counter1 (clk, reset, c_enable[1], q1);
    bcdcount counter2 (clk, reset, c_enable[2], q2);
endmodule

4-digit decimal counter（Countbcd）
Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.
You may want to instantiate or modify some one-digit decade counters.
設計一個16位的十進制BCD計數器（個位占4位，十位占4位，百位占4位，千位占4位），然後個位進位，十位進位，百位進位時，都輸出一個使能信號。

module top_module ( 
 input clk, 
 input reset,   // Synchronous active-high reset
 output [3:1] ena, 
 output [15:0] q); 
 reg [3:0]	ones; 
 reg [3:0]	tens; 
 reg [3:0]	hundreds; 
 reg [3:0]	thousands; 
 always@(posedge clk)begin 
     if(reset)begin 
         ones <= 4'd0; 
     end 
     else if(ones == 4'd9)begin 
         ones <= 4'd0; 
     end 
     else begin 
         ones <= ones + 1'b1; 
     end 
     end 

     always@(posedge clk)begin 
         if(reset)begin 
             tens <= 4'd0; 
         end 
         else if(tens == 4'd9 && ones == 4'd9)begin 
             tens <= 4'd0; 
         end 
         else if(ones == 4'd9) begin 
             tens <= tens + 1'b1; 
             end 
         end 

     always@(posedge clk)begin 
         if(reset)begin 
             hundreds <= 4'd0; 
         end 
         else if(hundreds == 4'd9 && tens == 4'd9 && ones == 4'd9)begin 
             hundreds <= 4'd0; 
         end 
         else if(tens == 4'd9 && ones == 4'd9) begin 
             hundreds <= hundreds + 1'b1; 
         end 
         end 

     always@(posedge clk)begin 
         if(reset)begin 
             thousands <= 4'd0; 
         end 
         else if(thousands == 4'd9 && hundreds == 4'd9 && tens == 4'd9 && ones == 4'd9)begin 
             thousands <= 4'd0; 
             end 
         else if(hundreds == 4'd9 && tens == 4'd9 && ones == 4'd9) begin 
         thousands <= thousands + 1'b1; 
         end 
         end 
     assign q = {thousands, hundreds, tens, ones}; 
     assign ena[1] = (ones == 4'd9) ? 1'b1 : 1'b0; 
     assign ena[2] = (tens == 4'd9 && ones == 4'd9) ? 1'b1 : 1'b0;
    a
    ssign ena[3] = (hundreds == 4'd9 && tens == 4'd9 && ones == 4'd9) ? 1'b1 : 1'b0; 

 endmodule


Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).
reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.
The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.
Count Clock
module top_module(
    input clk, 
 input reset,
    input ena, 
 output pm, 
 output [7:0] hh, 
 output [7:0] mm, 
 output [7:0] ss); 

 always@(posedge clk ) //處理秒00-59
     if (reset) 
        ss <= 8'h00; 
     else if(ena) begin 
         if(ss == 8'h59) 
             ss <= 8'h00; 
     else   begin
            if(ss[3:0] < 4'h9)
             ss[3:0] <= ss[3:0] + 1'h1; 
     else
              begin 
         ss[3:0] <= 0; 
         ss[7:4] <= ss[7:4] + 1'h1; 
     end 
     end 
  end 

 always@(posedge clk) //處理分 00-59
     if (reset) 
        mm <= 8'h00; 
     else if(ena) begin 
         if(ss == 8'h59) 
             if(mm == 8'h59) 
                 mm <= 8'h00; 
             else  
                if(mm[3:0] < 4'h9)
                                        begin 
                 mm[3:0] <= mm[3:0] + 1'h1; 
              end 
             else
                                        begin 
                 mm[3:0] <= 0; 
                 mm[7:4] <= mm[7:4] + 1'h1; 
     end 
 end 


 always@(posedge clk ) //處理時 00-12
     if (reset) 
        hh <= 8'h12; 
     else if(ena) begin 
         if(mm == 8'h59 && ss == 8'h59) begin 
             if(hh == 8'h12) 
                 hh <= 8'h01; 
             else  
                if(hh[3:0] < 4'h9)
                                        begin 
                 hh[3:0] <= hh[3:0] + 1'h1; 
             end 
             else
                                        begin 
                 hh[3:0] <= 0; 
                 hh[7:4] <= hh[7:4] + 1'h1; 
             end 
         end 
  end 


 always@(posedge clk ) //處理上午下午 AM/PM
         if (reset) 
            pm <= 0; 
         else if(hh ==  8'h11 && mm == 8'h59 && ss == 8'h59) 
         pm =!pm; 

endmodule