HDLBits Shift Register(Exams/m2014 q4k) LUT

 HDLBits  Shift Register(Exams/m2014 q4k) LUT

In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function.

First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).

實現的是一個和 8x1 結構的存儲體相關的電路。存儲的輸入通過移入比特進行，存儲的讀取類似於傳統 RAM 中的隨機讀取，即可以指定讀出比特的位置，通過 3 個輸入端口指定讀取位置。

首先通過 8 個觸发器實現一個 8bit 深的移位寄存器。8個寄存器的輸出依次為 Q[0]...Q[7]。移位寄存器的輸入為 S，輸入首先會填充到 MSB（最高位），Q[0]。當 enable 信號控制移位，當其有效時輸入數據並移位。此外，該電路有三個輸入端口 A,B,C 以及輸出端口 Z。工作的功能如下：當 ABC = 000 時，Z = Q[0],當 ABC = 001 時，Z = Q[1],以此類推。你的電路中只能包括一個 8bit 移位寄存器以及一個多路選擇器。（這就是個三輸入查找表 LUT 電路）

module top_module (
    input clk,
    input enable,
    input S,
    input A, B, C,
    output Z ); 
    
    reg [7:0] Q;
    always@(posedge clk)begin
        if(enable)begin
            Q <= {Q[6:0], S};
        end
    else begin
            Q <= Q;
        end
    end
    always@(*)begin
        case({A, B, C})
            3'b000: Z = Q[0];
            3'b001: Z = Q[1];
            3'b010: Z = Q[2];
            3'b011: Z = Q[3];
            3'b100: Z = Q[4];
            3'b101: Z = Q[5];
            3'b110: Z = Q[6];
            3'b111: Z = Q[7];
        endcase
    end
endmodule