DE2-115 Shift Register(Exams/m2014 q4b)

 DE2-115  Shift Register(Exams/m2014 q4b)

Consider the n-bit shift register circuit shown below:

實現下圖中的 n bit 移位暫存器電路

Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 16. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2-115 board.

• Connect the R inputs to the SW [15:0] switches,
• clk to KEY[0],
• E to KEY[1],
• L to KEY[2], and
• w to KEY[3].
• Connect the outputs to the red lights LEDR[15:0].

(Reuse your MUXDFF from exams/2014_q4a.)

module m2014q4b (
    input [17:0] SW,
    input [3:0] KEY,
    output [15:0] LEDR
); //
    wire [15:0] w_input = {KEY[3],LEDR[15],LEDR[14],LEDR[13],
    LEDR[12],LEDR[11],LEDR[10],LEDR[9],LEDR[8],LEDR[7],
    LEDR[6],LEDR[5],LEDR[4],LEDR[3],LEDR[2],LEDR[1]};
    generate 
        genvar i;
        for(i=0;i<16;i=i+1) begin:muxdff
            MUXDFF (
        .clk(KEY[0]),
            .w(w_input[i]), 
            .R(SW[i]),    //load sw[15:0] data
        .E(SW[17]),
        .L(SW[16]),
            .Q(LEDR[i]) );
        end
    endgenerate
endmodule

module MUXDFF (
    input clk,
    input w, R, E, L,
    output reg Q
);
    always@(posedge clk)begin
        case({E,L})
            2'b00: Q <= Q;
            2'b01: Q <= R;  //load sw[15:0] data
            2'b10: Q <= w; //load KEY[3] data
            2'b11: Q <= R;  //load sw[15:0] data        
        endcase
    end
endmodule