HDLBits Simple FSM1 / Fsm1s

HDLBits Simple FSM1 / Fsm1s 

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1, but using synchronous reset.同步式 reset.

// Note the Verilog-1995 module declaration syntax here:
module top_module(clk, reset, in, out);
    input clk;
    input reset;    // Synchronous reset to state B
    input in;
    output out;//  

    reg out;
    // Fill in state name declarations
    reg present_state, next_state;

    always @(posedge clk) begin
        if (reset) begin  
               // Fill in reset logic
        end else begin
            case (present_state)
                    // Fill in state transition logic
            endcase
            // State flip-flops
            present_state = next_state;   
            case (present_state)
                // Fill in output logic
            endcase
        end
    end

endmodule

與非同步式的差別

同步式 always @(posedge clk) begin     // State flip-flops with asynchronous reset      if (reset)             state<=B;         else            state<=next_state;         end

非同步式 always @(posedge clk, posedge areset) begin     // State flip-flops with asynchronous reset         if (areset)             state<=B;         else            state<=next_state;         end

// Note the Verilog-1995 module declaration syntax here:

module top_module(clk, reset, in, out);

    input clk;

    input reset;    // Synchronous reset to state B

    input in;

    output out;//  

    reg out;

    parameter A=0, B=1; 

    reg state, next_state;

    // This is a sequential always block

    always @(posedge clk) begin    

        // State flip-flops with asynchronous reset

    if (reset) 

           state<=B;

        else

           state<=next_state;    

    end

    always @(*) begin    // This is a combinational always block

        // State transition logic

        case(state)

            B: next_state= in? B:A;

            A: next_state= in? A:B;

        endcase

    end

    // Output logic

    // assign out = (state == ...);

    always@(*) begin

   case (state)

A: out = 1'b0;

B: out = 1'b1;

endcase

    end             

endmodule