HDLBits Shift Register(Exams/m2014 q4b)

 HDLBits Shift Register(Exams/m2014 q4b)

Consider the n-bit shift register circuit shown below:

實現下圖中的 n bit 移位暫存器電路

Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.

• Connect the R inputs to the SW [3:0] switches,
• clk to KEY[0],
• E to KEY[1],
• L to KEY[2], and
• w to KEY[3].
• Connect the outputs to the red lights LEDR[3:0].

(Reuse your MUXDFF from exams/2014_q4a.)

module top_module (
    input [3:0] SW,
    input [3:0] KEY,
    output [3:0] LEDR
); //
    wire [3:0] w_input = {KEY[3],LEDR[3],LEDR[2],LEDR[1]};
    generate 
        genvar i;
        for(i=0;i<4;i=i+1) begin:muxdff
            MUXDFF (
        .clk(KEY[0]),
            .w(w_input[i]),
            .R(SW[i]),
        .E(KEY[1]),
        .L(KEY[2]),
            .Q(LEDR[i]) );
        end
    endgenerate
endmodule
//module MUXDFF (...);
module MUXDFF (
    input clk,
    input w, R, E, L,
    output Q
);
    always@(posedge clk)begin
        case({E,L})
            2'b00: Q <= Q;
            2'b01: Q <= R;
            2'b10: Q <= w;
            2'b11: Q <= R;          
        endcase
    end
endmodule