DE2-115 16bits shift register (right shift)

DE2-115 16bits shift register (right shift)

Build a 16-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.

• areset: Resets shift register to zero.
• load: Loads shift register with data[15:0] instead of shifting.
• ena: Shift right (q[15] becomes zero, q[0] is shifted out and disappears).
• q: The contents of the shift register.

If both the load and ena inputs are asserted (1), the load input has higher priority.

//Filename: ShiftRegister_16bit.v
module ShiftRegister_16bit (
 input  CLOCK_50,
 input  [17:0] SW,
 input  [3:0]  KEY,
 output [15:0] LEDR
);
wire  clk_1;
// 1Hz clock
//divn # (.WIDTH(26), .N(50_000000))
divn # (.WIDTH(26), .N(15_000000))
u0 (  .clk(CLOCK_50), .rst_n(KEY[0]), .o_clk(clk_1));
top_module u1( 
 .clk(clk_1), 
 .areset(KEY[0]),
 .load(SW[16]),
 .ena(SW[17]),
 .data(SW[15:0]),
 .q(LEDR[15:0]) // output  
 ); 
endmodule

//===================================

module top_module(

    input clk,

    input areset,  // async active-high reset to zero

    input load,

    input ena,

    input [15:0] data,

    output reg [15:0] q); 

    always@(posedge clk or negedge areset)begin

        if(!areset)begin

           q <= 'd0; 

        end

        else if(load)begin

           q <= data; 

        end

        else if(ena)begin

            q <= {1'd0,q[15:1]};

        end

    end

endmodule

//===================================

/*

Filename  : divn.v

*/

module divn  (

  input  clk,

  input  rst_n,

  output o_clk

);

parameter WIDTH = 3;

parameter N  = 6;

reg [WIDTH-1:0] cnt_p;

reg [WIDTH-1:0] cnt_n;

reg  clk_p;

reg  clk_n;

assign o_clk = (N == 1) ? clk : (N[0]) ? (clk_p | clk_n) : (clk_p);

always@(posedge clk or negedge rst_n) begin

if (!rst_n)

cnt_p <= 0;

else if (cnt_p == (N-1))

cnt_p <= 0;

else

cnt_p <= cnt_p + 1;

end

always@(posedge clk or negedge rst_n) begin

if (!rst_n)

clk_p <= 1;

else if (cnt_p < (N>>1))

clk_p = 1;

else

clk_p = 0;

end

always@(negedge clk or negedge rst_n) begin

if (!rst_n)

cnt_n <= 0;

else if (cnt_n == (N-1))

cnt_n <= 0;

else

cnt_n <= cnt_n + 1;

end

always@(negedge clk or negedge rst_n) begin

if (!rst_n)

clk_n <= 1;

else if (cnt_n < (N>>1))

clk_n = 1;

else

clk_n = 0;

end

endmodule

//===================================