DE2-115 16-bit left/right rotator

DE2-115 16-bit left/right rotator 

Build a 16-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.

• load: Loads shift register with data[15:0] instead of rotating.
• ena[1:0]: Chooses whether and which direction to rotate.
  • 2'b01 rotates right by one bit
  • 2'b10 rotates left by one bit
  • 2'b00 and 2'b11 do not rotate.
• q: The contents of the rotator.

//Filename: Rotate16.v

module Rotate16 (

 input  CLOCK_50,

 input  [17:0] SW,

 input  [3:0]  KEY,

 output [15:0] LEDR

);

wire  clk_1;

// 1Hz clock

//divn # (.WIDTH(26), .N(50_000000))

divn # (.WIDTH(26), .N(15_000000))

u0 (  .clk(CLOCK_50), .rst_n(KEY[0]), .o_clk(clk_1));

top_module u1( 

 .clk(clk_1), 

 .load(KEY[0]),

 .ena(SW[17:16]),

 .data(SW[15:0]),

 .q(LEDR[15:0]) // output  

 ); 

endmodule

//===================================

module top_module(

    input clk,

    input load,

    input [1:0] ena,

    input [15:0] data,

    output reg [15:0] q); 

    

    always@(posedge clk) begin

        if (!load) begin

            q<=data;

    end

        else begin

        case(ena)

            2'b00 : q<=q;

            2'b11 : q<=q;

            2'b01 : q={q[0],q[15:1]};

            2'b10 : q={q[14:0],q[15]};

        endcase

    end

    end   

endmodule

//===================================

/*

Filename  : divn.v

*/

module divn  (

  input  clk,

  input  rst_n,

  output o_clk

);

parameter WIDTH = 3;

parameter N  = 6;

reg [WIDTH-1:0] cnt_p;

reg [WIDTH-1:0] cnt_n;

reg  clk_p;

reg  clk_n;

assign o_clk = (N == 1) ? clk : (N[0]) ? (clk_p | clk_n) : (clk_p);

always@(posedge clk or negedge rst_n) begin

if (!rst_n)

cnt_p <= 0;

else if (cnt_p == (N-1))

cnt_p <= 0;

else

cnt_p <= cnt_p + 1;

end

always@(posedge clk or negedge rst_n) begin

if (!rst_n)

clk_p <= 1;

else if (cnt_p < (N>>1))

clk_p = 1;

else

clk_p = 0;

end

always@(negedge clk or negedge rst_n) begin

if (!rst_n)

cnt_n <= 0;

else if (cnt_n == (N-1))

cnt_n <= 0;

else

cnt_n <= cnt_n + 1;

end

always@(negedge clk or negedge rst_n) begin

if (!rst_n)

clk_n <= 1;

else if (cnt_n < (N>>1))

clk_n = 1;

else

clk_n = 0;

end

endmodule

//===================================