Verilog Gate primitives

Gate primitives

There are two classes of gate primitives:

Single input gate primitives

not, buf gates

module buf_not_gates (input a, b, output c, d);
  buf (c, a, b);   // c is the output, a and b are inputs
  not (d, a, b);  // d is the output, a and b are inputs
endmodule

module buf_not_gates_tb;
  reg a, b;
  wire c, d;
  buf_not_gates Instance0 (a, b, c,d);
  initial begin
    a = 0; b = 0;
 #1 a = 0; b = 1; 
 #1 a = 1; b = 0;
 #1 a = 1; b = 1;
  end
  initial begin
    $monitor ("T=%t| a=%b |b=%b| c(buf)=%b |d(not)=%b", $time, a, b, c, d);
  end
endmodule

bufif/notif gates

module bufif_notif_gates (output c, d, input a, b);
  bufif (c, a, b);   // c is the output, a and b are inputs
  notif (d, a, b);  // d is the output, a and b are inputs
endmodule

module bufif_notif_gates_tb;
  reg a, b;
  wire c, d;
  bufif_notif_gates Instance0 (c, d, a, b);
  initial begin
    a = 0; b = 0;
 #1 a = 0; b = 1; 
 #1 a = 1; b = 0;
 #1 a = 1; b = 1;
  end
  initial begin
    $monitor ("T=%t| a=%b |b=%b| c(bufif)=%b |d(notif)=%b", $time, a, b, c, d);
  end
endmodule

Multiple input gate primitives

AND/OR/XOR gates

module and_or_xor_gates (output c, d, e, input a, b);
  and (c, a, b);   // c is the output, a and b are inputs
  or  (d, a, b);  // d is the output, a and b are inputs
  xor (e, a, b);   // e is the output, a and b are inputs
endmodule

module and_or_xor_gates_tb;
reg a, b;
wire c, d, e;
and_or_xor_gates Instance0 (c, d, e, a, b);
 initial begin
      a = 0; b = 0;
   #1 a = 0; b = 1; 
   #1 a = 1; b = 0;
   #1 a = 1; b = 1;
 end
 initial begin
   $monitor ("T=%t |a=%b |b=%b |c(and)=%b |d(or)=%b |e(xor)=%b", $time, a, b, c, d, e);
 end
endmodule

NAND/NOR/XNOR gates

module nand_nor_xnor_gates (output c, d, e, input a, b);
 nand (c, a, b); // c is the output, a and b are inputs 
 nor (d, a, b); // d is the output, a and b are inputs 
 xnor (e, a, b); // e is the output, a and b are inputs
endmodule 

module nand_nor_xnor_gates_tb;
reg a, b;
wire c, d, e;
nand_nor_xnor_gates Instance0 (c, d, e, a, b);
  initial begin
    a = 0; b = 0;
 #1 a = 0; b = 1; 
 #1 a = 1; b = 0;
 #1 a = 1; b = 1;
end
  initial begin
    $monitor ("T=%t |a=%b |b=%b |c(nand)=%b |d(nor)=%b |e(xnor)=%b", $time, a, b, c, d, e);
  end
endmodule

 more than two inputs.

module all_gates (output x1, y1, z1, x2, y2, z2 , input a, b, c, d);
  and (x1, a, b, c, d);   // x1 is the output, a, b, c, d are inputs
  or  (y1, a, b, c, d);  // y1 is the output, a, b, c, d are inputs
  xor (z1, a, b, c, d);   // z1 is the output, a, b, c, d are inputs
  nand (x2, a, b, c, d); // x2 is the output, a, b, c, d are inputs
  nor (y2, a, b, c, d); // y2 is the output, a, b, c, d are inputs 
  xnor (z2, a, b, c, d); // z2 is the output, a, b, c, d are inputs
endmodule

Gate Delays

Rise delay Fall delay Turn off delay

primitive_gate #(rise delay, fall delay, turn-off delay) gate_instatiation (outputs, inputs);

and #(2) and_gate_2 (out, in0, in1);       // all delay values are 2-time units
nand #(3,4,5) nand_gate_2 (out, in0, in1); // rise delay = 3, fall delay = 4, and turn-off delay = 5.
or #(3,4) or_gate_2 (out, in0, in1);       // rise delay = 3, fall delay = 4, and turn-off delay = min(3,4) = 3.

nand #(3:4:5,4:5:6,5:6:7) nand_gate_2 (out, in0, in1); // rise delay: min=3, typ=4, max=5, fall delay: min=4, typ=5, max=6, turn-off delay: min=5, typ=6, max=7.