Verilog Code for AND Gate – All modeling styles

Verilog Code for AND Gate – All modeling styles

源自於https://www.technobyte.org/verilog-and-gate/

Gate Level modeling

module AND_2(output Y, input A, B);
    and(Y, A, B); 
endmodule

Data flow modeling

module AND_2_data_flow (output Y, input A, B);

assign Y = A & B; 
endmodule

Behavioral Modelling

AND gate’s truth table

A	B	Y(A and B)
0	0	0
0	1	0
1	0	0
1	1	1

Equation from the truth table

Simply by minimization, (or you may arrive by k-maps), we can state that:

Y = A.B or say Y = A & B.

module AND_2_behavioral (output reg Y, input A, B);
always @ (A or B) begin
    if (A == 1'b1 & B == 1'b1) begin
        Y = 1'b1;
    end
    else 
        Y = 1'b0; 
end
endmodule

RTL schematic of the AND gate

Testbench of the AND gate using Verilog

`include "AND_2_behavioral.v"

`timescale 100ns/1ns
module AND_2_behavioral_tb;
reg A, B;
wire Y;
AND_2_behavioral Indtance0 (Y, A, B);
initial begin
    A = 0; B = 0;
 #1 A = 0; B = 1;
 #1 A = 1; B = 0;
 #1 A = 1; B = 1;
end
initial begin
    $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
    $dumpfile("dump.vcd");
    $dumpvars();
end
endmodule