Verilog for Loop ---8 bit shift register
module loop_shift_reg (clk,rstn,load_val,load_en,op);
input clk; // Clock input
input rstn; // Active low reset input
input [7:0]load_val; // Load value
input load_en; // Load enable
output reg [7:0] op; // Output register value
integer i;
// At posedge of clock, if reset is low set output to 0
// If reset is high, load new value to op if load_en=1
// If reset is high, and load_en=0 shift register to left
always @ (posedge clk) begin
if (!rstn) begin
op <= 0;
end
else begin
// If load_en is 1, load the value to op
// else keep shifting for every clock
if (load_en) begin
op <= load_val;
end
else begin
for (i = 0; i <=6; i=i+1) begin
op[i+1]<=op[i];
end
op[0]<=op[7];
end
end // else begin
end //always @ (posedge clk) begin
endmodule
`timescale 100 ns/1 ns
module tb;
reg clk;
reg rstn;
reg [7:0] load_val;
reg load_en;
wire [7:0] op;
// Setup DUT clock
always #10 clk = ~clk;
// Instantiate the design
loop_shift_reg UUT ( .clk(clk),
.rstn (rstn),
.load_val (load_val),
.load_en (load_en),
.op (op));
initial begin
// 1. Initialize testbench variables
clk = 0;
rstn = 0;
load_val = 8'h01;
load_en = 0;
// 2. Apply reset to the design
repeat (2) @ (posedge clk);
rstn <= 1;
repeat (3) @ (posedge clk);
// 3. Set load_en for 1 clk so that load_val is loaded
load_en <= 1;
repeat(2) @ (posedge clk);
load_en <= 0;
// 4. Let design run for 20 clocks and then finish
repeat (12) @ (posedge clk);
$stop;
end
endmodule
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