以Verilog 設計一個數位電路 (EX_202)--- always行為模式 --2x1 mux 電路

以Verilog 設計一個數位電路 (EX_202)--- always行為模式 --2x1 mux 電路

`timescale 1 ns/1 ns

module EX_202 (a, b, c, sel);
input a, b, sel;
output c;
reg c;

// non-behavioral writing style in EX_104 is also listed for
// comparison. c should be declared as wire in
// non-behavioral writing style.
//
// wire c;
//
// assign c = ( sel == 1'b1 ) ? a : b;

always@(sel or a or b)
begin
if (sel==1'b1)
  c = a;
else
  c = b;
end

endmodule

`timescale 100 ns/1 ns

module testbench;

reg     sel ,a, b ;

wire c;

integer i;

EX_202 UUT(

.a(a),

.b(b),

.c(c),

.sel(sel) );

initial

begin

for (i=0;i<=7;i=i+1) begin

{sel,a,b}=i;

#20;

end

#20;

$stop;

end

endmodule