以Verilog 設計一個數位電路 (11)--- unsigned , signed + *

以Verilog 設計一個數位電路 (11)--- unsigned , signed + * 

Hex value:
35 × 76 = 186E
Hex value:
186E + 9a = 1908

`timescale 1 ns/1 ns

module EX_111 (a, b, c, k_usgn, k_sgn);
input [7:0] a, b, c;
output [15:0] k_usgn, k_sgn;
wire [15:0] k_usgn, k_sgn;

wire [7:0] d_usgn, e_usgn, d_sgn, e_sgn;
wire [15:0] tmp_usgn, tmp_sgn;

// for unsigned operation
assign tmp_usgn = a * b;

assign {d_usgn, e_usgn} = tmp_usgn + {8'h00,c};

assign k_usgn = {d_usgn, e_usgn};


// for signed operation
assign tmp_sgn = {{8{a[7]}},a} * {{8{b[7]}},b};

assign {d_sgn , e_sgn } = tmp_sgn  + {{8{c[7]}},c};

assign k_sgn = {d_sgn, e_sgn};


endmodule

//================================

`timescale 100 ns/1 ns

module testbench;

reg [7:0] a, b, c;

wire[15:0] k_usgn, k_sgn;

EX_111 UUT(

.a(a),

.b(b),

.c(c),

.k_usgn(k_usgn),

.k_sgn(k_sgn) );

initial

begin

 a   = 8'h35; // Time = 0

 b   = 8'h76;

 c   = 8'h9a;

 #50; // Time = 50

 a   = 8'h18;

 b   = 8'h86;

 c   = 8'h51;

 #50;

 $stop;

end

endmodule