以Verilog 設計一個數位電路 (5)---Nested MUX

 以Verilog 設計一個數位電路 (5)---Nested MUX

//================================
`timescale 1 ns/1 ns

module EX_105 (a, b, c, d, e, f, sel1, sel2, sel3);
input [3:0] a, b, d, e;
input sel1, sel2, sel3;

output [3:0] c, f;
wire [3:0] c, f;

assign c = ( sel1 ) ? a :
    ( sel2 ) ? b :
    ( sel3 ) ? d : e;

assign f = ( sel1 ) ? ((sel2) ? a : b) :
    ((sel3) ? d : e) ;

endmodule

//================================

`timescale 100 ns/1 ns

module testbench;
reg [3:0] a, b, d, e;
reg sel1, sel2, sel3;
wire [3:0] c, f;

EX_105 UUT(
.a(a),
.b(b),
.d(d),
.e(e),
.sel1(sel1),
.sel2(sel2),
.sel3(sel3),
.c(c),
.f(f) );
initial
begin
 a    = 4'b1010; // Time = 0
 b    = 4'b1011;
 d    = 4'b1101;
 e    = 4'b1110;
 sel1 = 1'b0; sel2 = 1'b0; sel3 = 1'b0;
 #50; // Time = 50
 sel1 = 1'b0; sel2 = 1'b0; sel3 = 1'b1;
 #50; // Time = 100
 sel1 = 1'b0; sel2 = 1'b1; sel3 = 1'b0;
 #50; // Time = 150
 sel1 = 1'b0; sel2 = 1'b1; sel3 = 1'b1;
 #50; // Time = 200
 sel1 = 1'b1; sel2 = 1'b0; sel3 = 1'b0;
 #50; // Time = 250
 sel1 = 1'b1; sel2 = 1'b0; sel3 = 1'b1;
 #50; // Time = 300
 sel1 = 1'b1; sel2 = 1'b1; sel3 = 1'b0;
 #50; // Time = 300
 sel1 = 1'b1; sel2 = 1'b1; sel3 = 1'b1;
 #50;
  $stop;
end
endmodule