以Verilog 設計一個數位電路 (EX203)--- always -- mux if..esle 電路

以Verilog 設計一個數位電路 (EX203)--- always --  mux if..esle 電路

`timescale 1 ns/1 ns

module ex_203 (a, b, c, d, e, f, sel1, sel2, sel3);
input [3:0] a, b, d, e;
input sel1, sel2, sel3;
output [3:0] c, f;
reg [3:0] c, f;

// non-behavioral writing style in EX_105 is also listed for
// comparison. c and f should be declared as wire in
// non-behavioral writing style.
//
// wire [3:0] c, f;
//
// assign c = ( sel1 ) ? a :
//            ( sel2 ) ? b :
//            ( sel3 ) ? d : e;

always@(sel1 or sel2 or sel3 or a or b or d or e)
begin
if (sel1)
  c = a;
else if (sel2)
       c = b;
     else if (sel3)
            c = d;
          else
            c = e;
end

// non-behavioral writing style in EX_105 is also listed for
// comparison.
//
// assign f = ( sel1 ) ? ((sel2) ? a : b) :
//                       ((sel3) ? d : e) ;

always@(sel1 or sel2 or sel3 or a or b or d or e)
begin
if (sel1)
  if (sel2)
    f = a;
  else
    f = b;
else
  if (sel3)
    f = d;
  else
    f = e;
end

endmodule

`timescale 100 ns/1 ns

module testbench;

reg [3:0]a, b, d, e;

reg sel1, sel2, sel3;

wire [3:0] c, f;

integer i;

ex_203 UUT (

.a(a), .b(b), .d(d), .e(e),

.sel1(sel1), .sel2(sel2),

.sel3(sel3), .c(c), .f(f) );

initial

begin

 a    = 4'b1010; // Time = 0

 b    = 4'b1011;

 d    = 4'b1101;

 e    = 4'b1110;

 for (i=0;i<=7;i=i+1) begin

{sel1,sel2,sel3}=i;

#20;

 end

 #20;

 $stop;

end

endmodule