module D_FlipFlop (CLK,D,EN,RST,Q1,Q1bar,Q2,Q2bar,Q3,Q4);
input CLK,D,EN,RST;
output Q1, Q1bar, Q2, Q2bar, Q3 ,Q4 ;
D_latch_behavior U1(.D(D), .Enable(EN), .Q(Q1), .Qbar(Q1bar));
d_latch_dataflow U2(.d(D), .en(EN), .q(Q2), .qn(Q2bar));
d_ff U3(.clk(CLK), .rst_n(RST), .en(EN), .d(D), .q(Q3));
D_ff_behavior U4(.D(D), .Clk(CLK), .Q(Q4));
endmodule
module D_latch_behavior (input D, input Enable, output reg Q, output reg Qbar);
always @ (D or Enable)
if(Enable)
begin
Q <= D; Qbar <= ~D;
end
endmodule
module d_latch_dataflow (
input d,
input en,
output q,
output qn
);
assign q = (en) ? d : q;
assign qn=~q;
endmodule
module d_ff (
input clk,
input rst_n,
input en,
input d,
output reg q
);
always@(posedge clk or negedge rst_n)
if (!rst_n)
q <= 0;
else if (en)
q <= d;
endmodule
module D_ff_behavior (input D, input Clk, output reg Q);
always @ (posedge Clk)
if(Clk)
begin
Q <= D;
end
endmodule
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
//(CLK,D,EN,RST,Q1,Q1bar,Q2,Q2bar,Q3.Q4);
reg CLK,D,EN,RST;
wire Q1,Q1bar,Q2,Q2bar,Q3,Q4;
D_FlipFlop UUT (CLK,D,EN,RST,Q1,Q1bar,Q2,Q2bar,Q3,Q4);
initial begin
$monitor(CLK,D,EN,RST,Q1,Q1bar,Q2,Q2bar,Q3,Q4);
// Initialize Inputs
D = 0;EN=1;RST=1;CLK=0;
// Add stimulus here
#100 D = 1;
#100 D = 1; EN=0;
#100 D = 0; EN=1;
#100 D = 1; RST=0;
#100 D = 0; RST=1;
#100 D = 1;
#100 D = 0; EN=0;
#100 $stop;
end
always #10 CLK <= ~CLK;
endmodule
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