//0,1,2,3,4,5,6,7,8,9,0,1...BCD計數器
//KEY[0]= 重置 reset
//KEY[3]= 計數脈波 手動計數 LEDG[0:3] = BCD計數器輸出
//1Hz 計數脈波 自動計數 LEDG[4:7] = BCD計數器輸出
//=============================================
//Top module
//=============================================
//0,1,2,3,4,5,6,7,8,9,0,1...BCD計數器
//KEY[0]= 重置 reset
//KEY[3]= 計數脈波 手動計數 LEDG[0:3] = BCD計數器輸出
//1Hz 計數脈波 自動計數 LEDG[4:7] = BCD計數器輸出
//=============================================
module bcd_cnt_1digit_led(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR, // LED Red
inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA // LCD Data bus 8 bits
);
// Send switches to red leds
assign LEDR = SW;
//assign LEDG[8:0] = 9'h000; //不能設定assigment
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;
wire [7:0] segout0; //HEX 0
wire [7:0] segout3; //HEX 1
// All inout port turn to tri-state
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
// Setup clock divider
wire [6:0] myclock;
wire RST;
assign RST = KEY[0];
clock_divider cdiv(CLOCK_50,RST,myclock);
reg timer_state0 , timer_state1;
wire [3:0] digit0;
wire [3:0] digit1;
wire [3:0] ovr;
wire clock0, clock1 ,reset, pulse;
assign clock0 = (timer_state0? myclock[0]: 1'b0);
assign clock1 = (timer_state1? myclock[0]: 1'b0);
assign reset = (~pulse & RST);
decimal_counter count0(digit0,ovr[0],clock0,reset);
decimal_counter count1(digit1,ovr[1],clock1,reset);
assign LEDG[0]=digit0[0];
assign LEDG[1]=digit0[1];
assign LEDG[2]=digit0[2];
assign LEDG[3]=digit0[3];
assign LEDG[4]=digit1[0];
assign LEDG[5]=digit1[1];
assign LEDG[6]=digit1[2];
assign LEDG[7]=digit1[3];
always @ (negedge KEY[3] or negedge RST)
begin
if (!RST) timer_state0 <= 1'b0;
else timer_state0 <= ~timer_state0;
end
always @ (negedge myclock[0] or negedge RST)
begin
if (!RST) timer_state1 <= 1'b0;
else timer_state1 <= ~timer_state1;
end
_7seg UUT0(.hex((digit0[3:0])),.seg(segout0));
_7seg UUT3(.hex((digit1[3:0])),.seg(segout3));
assign HEX0=segout0[6:0];
assign HEX3=segout3[6:0];
endmodule
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
module clock_divider(CLK,RST,clock);
input CLK,RST;
output [6:0] clock;
wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;
assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
endmodule
module divide_by_10(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count+1'b1;
end
else
begin
count <= 3'b000;
Q <= ~Q;
end
end
endmodule
module divide_by_50(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 5'b00000;
end
else if (count < 24)
begin
count <= count+1'b1;
end
else
begin
count <= 5'b00000;
Q <= ~Q;
end
end
endmodule
module decimal_counter(A,OVERFLOW,CLK,RST);
input CLK, RST;
output OVERFLOW;
output [3:0] A;
reg OVERFLOW;
reg [3:0] A;
always @ (posedge CLK or negedge RST)
if (~RST) begin
OVERFLOW <= 1'b0;
A <= 4'b0000;
end
else if (A<9) begin
A <= A + 1'b1;
OVERFLOW <= 1'b0;
end
else begin
A <= 4'b0000;
OVERFLOW <= 1'b1;
end
endmodule
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