Verilog code for Traffic light controller

//traffic_light_GYR//

module traffic_light_GYR(clk_in,Ring_clk,G,Y,R);

 input clk_in; // input clock on FPGA

 output Ring_clk,G,Y,R; // output clock after dividing the input clock by divisor

 wire   Ring_clk;

 wire    G,Y,R;

 wire   g1,y1,r1;

 wire   [9:0]qout;

//clock_divide_4 (input clk,input rst_n,output reg o_clk);

// johnson_cnt_10(clock,reset,q);

 clock_divide_4 U1(.clk(clk_in),.rst_n(1'b1),.o_clk(Ring_clk));

 johnson_cnt_10 U2(.clock(Ring_clk),.reset(1'b0),.q(qout));

 assign g1 = (clk_in & qout[3]) | qout[0]| qout[1] | qout[2] ;

 assign y1= qout[4]; 

 assign r1= qout[5]| qout[6] | qout[7]| qout[8] | qout[9];

 assign G=g1;

 assign Y=y1;

 assign R=r1;

endmodule

//============================================================

module johnson_cnt_10(clock,reset,q);

   input clock;

   input reset;

   output [9:0] q;

   reg[9:0] a=10'b0000000001;

    always @(posedge clock)

      if (reset)

        a = 10'b0000000001;

      else

        begin

        a <=  a<<1; // Notice the blocking assignment

        a[0]<=a[9];

        end

    assign q = a;

  endmodule

//============================================================

module clock_divide_4 (input clk,input rst_n,output reg o_clk);

 reg [1:0] cnt;

always@(posedge clk or negedge rst_n) begin

   if (!rst_n)

     cnt <= 0;

   else if (cnt == 3) // 0 ~ 3

     cnt <= 0;

   else

     cnt <= cnt + 1;

 end

always@(posedge clk or negedge rst_n) begin

   if (!rst_n)

     o_clk <= 0;

   else if (cnt < 2) // 0 ~ 1

     o_clk = 0;

   else              // 2 ~ 3

     o_clk = 1;   

 end

endmodule

`timescale 1ns/10ps

module Test_bench;

 reg clk_in;

 wire Ring_clk,G,Y,R;

traffic_light_GYR UUT ( 

   .clk_in(clk_in),

   .Ring_clk(Ring_clk),

   .G(G),

   .Y(Y),

   .R(R)   

 );

 initial begin

   clk_in   = 1'b0;

   #1500 $stop;

 end

 // 50MHz clk

 always #10 clk_in = ~clk_in;

endmodule