參考來源 https://www.fpga4fun.com/Opto3.html
//需 Import pin assignments DE2_115_pin_assignments
//The 7-segments display
//============================================
/*
module LED_7seg(
input clk,
output segA, segB, segC, segD, segE, segF, segG, segDP
);
// cnt is used as a prescaler
reg [23:0] cnt;
always @(posedge clk) cnt <= cnt+24'h1;
wire cntovf = &cnt;
// BCD is a counter that counts from 0 to 9
reg [3:0] BCD;
always @(posedge clk) if(cntovf) BCD <= (BCD==4'h9 ? 4'h0 : BCD+4'h1);
reg [7:0] SevenSeg;
always @(*)
case(BCD)
4'h0: SevenSeg = 8'b11111100;
4'h1: SevenSeg = 8'b01100000;
4'h2: SevenSeg = 8'b11011010;
4'h3: SevenSeg = 8'b11110010;
4'h4: SevenSeg = 8'b01100110;
4'h5: SevenSeg = 8'b10110110;
4'h6: SevenSeg = 8'b10111110;
4'h7: SevenSeg = 8'b11100000;
4'h8: SevenSeg = 8'b11111110;
4'h9: SevenSeg = 8'b11110110;
default: SevenSeg = 8'b00000000;
endcase
assign {segA, segB, segC, segD, segE, segF, segG, segDP} = SevenSeg;
endmodule
module LED_7seg(
input clk,
output segA, segB, segC, segD, segE, segF, segG, segDP
);
reg [23:0] cnt;
always @(posedge clk) cnt <= cnt+24'h1;
wire cntovf = &cnt;
reg [3:0] BCD_new, BCD_old;
always @(posedge clk) if(cntovf) BCD_new <= (BCD_new==4'h9 ? 4'h0 : BCD_new+4'h1);
always @(posedge clk) if(cntovf) BCD_old <= BCD_new;
reg [4:0] PWM;
wire [3:0] PWM_input = cnt[22:19];
always @(posedge clk) PWM <= PWM[3:0]+PWM_input;
wire [3:0] BCD = (cnt[23] | PWM[4]) ? BCD_new : BCD_old;
reg [7:0] SevenSeg;
always @(*)
case(BCD)
4'h0: SevenSeg = 8'b11111100;
4'h1: SevenSeg = 8'b01100000;
4'h2: SevenSeg = 8'b11011010;
4'h3: SevenSeg = 8'b11110010;
4'h4: SevenSeg = 8'b01100110;
4'h5: SevenSeg = 8'b10110110;
4'h6: SevenSeg = 8'b10111110;
4'h7: SevenSeg = 8'b11100000;
4'h8: SevenSeg = 8'b11111110;
4'h9: SevenSeg = 8'b11110110;
default: SevenSeg = 8'b00000000;
endcase
assign {segA, segB, segC, segD, segE, segF, segG, segDP} = SevenSeg;
endmodule
*/
//============================================
//需 Import pin assignments DE2_115_pin_assignments
module LED_7seg(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR, // LED Red
inout [35:0] GPIO_0,GPIO_1, // GPIO Connections
// LCD Module 16X2
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [2:0] mess, // MESSAGE STATUS (see lcd_test)
input [1:0] isServer // SERVER STATUS (see lcd_test)
);
// All inout port turn to tri-state
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
// turn LCD ON
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
// blank unused 7-segment digits
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;
wire [7:0] segout0; //HEX 0
wire [7:0] segout3; //HEX 1
// cnt is used as a prescaler
reg [23:0] cnt;
always @(posedge CLOCK_50) cnt <= cnt+24'h1;
wire cntovf = &cnt;
// BCD is a counter that counts from 0 to 9
reg [3:0] BCD;
always @(posedge CLOCK_50) if(cntovf) BCD <= (BCD==4'h9 ? 4'h0 : BCD+4'h1);
//====================================================
//Finally let's try a "smooth" counter (fades each digit into then next).
//====================================================
reg [26:0] cnt1;
always @(posedge CLOCK_50) cnt1 <= cnt1+30'h1;
wire cntovf1 = &cnt1;
reg [3:0] BCD_new, BCD_old;
always @(posedge CLOCK_50) if(cntovf1) BCD_new <= (BCD_new==4'h9 ? 4'h0 : BCD_new+4'h1);
always @(posedge CLOCK_50) if(cntovf1) BCD_old <= BCD_new;
reg [4:0] PWM;
wire [3:0] PWM_input = cnt1[26:23];
always @(posedge CLOCK_50) PWM <= PWM[3:0]+PWM_input;
wire [3:0] BCD1 = (cnt1[26] | PWM[4]) ? BCD_new : BCD_old;
_7seg UUT0(.hex((BCD[3:0])),.seg(segout0));
_7seg UUT3(.hex((BCD1[3:0])),.seg(segout3));
assign HEX0=segout0[6:0];
assign HEX3=segout3[6:0];
endmodule
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
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