使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台,設計SR Flip-Flop (master-slave)為例(Test Bench開發平台)
module sr_flip_flop_master_slave(Q, Qn, C, S, R);
output Q;
output Qn;
input C;
input S;
input R;
wire MQ; // The master's Q output.
wire MQn; // The master's Qn output.
wire Cn; // The clock input to the slave shall be the complement of the master's.
not(Cn, C);
sr_latch_gated master(MQ, MQn, C, S, R);
sr_latch_gated slave(Q, Qn, Cn, MQ, MQn);
endmodule // sr_flip_flop_master_slave
module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;
wire S1;
wire R1;
and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule // sr_latch_gated
output Qn;
input C;
input S;
input R;
wire MQ; // The master's Q output.
wire MQn; // The master's Qn output.
wire Cn; // The clock input to the slave shall be the complement of the master's.
not(Cn, C);
sr_latch_gated master(MQ, MQn, C, S, R);
sr_latch_gated slave(Q, Qn, Cn, MQ, MQn);
endmodule // sr_flip_flop_master_slave
module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;
wire S1;
wire R1;
and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule // sr_latch_gated
`timescale 10ns/10ps
module tb_sr_FF_master_slave;
reg tCLK;
reg tS;
reg tR;
wire tQ, tQn;
//module r_flip_flop_master_slave(Q, Qn, C, S, R);
sr_flip_flop_master_slave DUT(tQ, tQn, tCLK, tS, tR);
//instantiate counter to be tested.
initial
begin
#0 tCLK=1'b0; //tCLK;
#8 tS=1'b1;tR=1'b0;
#18 tS=1'b0;tR=1'b1;
#28 tS=1'b1;tR=1'b1;
#38 tS=1'b1;tR=1'b0;
#48 tS=1'b0;tR=1'b0;
#58 tS=1'b0;tR=1'b1;
#68 tS=1'b1;tR=1'b1;
#78 tS=1'b1;tR=1'b1;
#100 $stop;
end
always begin
#10 tCLK=~tCLK; //generate clock
end
endmodule
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