使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計 4X1 Multiplexer 為例(FPGA開發平台)

 使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計 4X1  Multiplexer 為例(FPGA開發平台)

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );

 input  [17:0] SW;   // toggle switches
 input  [7:0] KEY;       // Push bottom
 input  CLOCK_50;   //Clock 27MHz , 50Mhz
 output [17:0] LEDR;   // red  LEDS
 output [8:0] LEDG;   // green LEDs
 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
 output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
 inout  [35:0] GPIO;
 assign HEX0=7'b111_1111;
 assign HEX1=7'b111_1111;
 assign HEX2=7'b111_1111;
 assign HEX3=7'b111_1111;
 assign HEX4=7'b111_1111;
 assign HEX5=7'b111_1111;
 assign HEX6=7'b111_1111;
 assign HEX7=7'b111_1111;
 
 
//mux_4to1_assign ( input [3:0] a, // 4-bit input called a  
//                         input [3:0] b,     // 4-bit input called b  
//                         input [3:0] c,     // 4-bit input called c  
//                         input [3:0] d,     // 4-bit input called d  
//                         input [1:0] sel,   // input sel used to select between a,b,c,d  
//                         output [3:0] out); // 4-bit output based on input sel  
    
 mux_4to1_assign(SW[3:0],SW[7:4],SW[11:8],SW[15:12],SW[17:16],LEDR[3:0]);  
    
 endmodule

module mux_4to1_assign ( input [3:0] a, // 4-bit input called a  
                         input [3:0] b,     // 4-bit input called b  
                         input [3:0] c,     // 4-bit input called c  
                         input [3:0] d,     // 4-bit input called d  
                         input [1:0] sel,   // input sel used to select between a,b,c,d  
                         output [3:0] out); // 4-bit output based on input sel  
  
// When sel[1] is 0, (sel[0]? b:a) is selected and sel[1] is 1, (sel[0] ? d:c) is taken  
// If sel[0] is 0, a is sent to output, else b and if sel[0] is 0, c is sent to output, else d  
   assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a);  
  
endmodule