使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計8 bits binary to decimal為例(FPGA開發平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計8 bits binary to decimal為例(FPGA開發平台)

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );
 input  [17:0] SW;   // toggle switches
 input  [7:0] KEY;       // Push bottom
 input  CLOCK_50;   //Clock 27MHz , 50Mhz
 output [17:0] LEDR;   // red  LEDS
 output [8:0] LEDG;   // green LEDs
 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
 output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
 inout  [35:0] GPIO;
 //assign HEX0=7'b111_1111;
 //assign HEX1=7'b111_1111;
 //assign HEX2=7'b111_1111;
 assign HEX3=7'b111_1111;
 assign HEX4=7'b111_1111;
 assign HEX5=7'b111_1111;
 assign HEX6=7'b111_1111;
 assign HEX7=7'b111_1111;
 
 // module binary_to_decimal(
 // input[7:0] binary,
 // output reg [3:0] Hundreds,
 // output reg [3:0] Tens,
 // output reg [3:0] Ones,
 wire [11:0]w;
 //wire [7:0] segout0;   //HEX 0
 //wire [7:0] segout1;   //HEX 1
 //wire [7:0] segout2;   //HEX 2
 
 binary_to_decimal u0(SW[7:0],w[11:8],w[7:4],w[3:0]);
 //module hexto7segment(hex , seg);
 //   input  [3:0] hex;
 //   output [7:0] seg;
 
 assign LEDR[11:0]=w[11:0];
 hexto7segment u1 (w[11:8],HEX2);
 hexto7segment u2 (w[7:4],HEX1);
 hexto7segment u3 (w[3:0],HEX0);
   
endmodule 

module binary_to_decimal(
input[7:0] binary,
output reg [3:0] Hundreds,
output reg [3:0] Tens,
output reg [3:0] Ones
);
integer i;

always @(binary)
begin
//Set 100's , 10's and 1's to 0
Hundreds=4'd0;
Tens=4'd0;
Ones=4'd0;

for (i=7;i>=0;i=i-1)
begin
//add3 to columns >=5
if (Hundreds >=5)
Hundreds=Hundreds+3;
if (Tens >=5)
Tens=Tens+3;
if (Ones >=5)
Ones=Ones+3;
//shift left one
Hundreds=Hundreds<<1;
Hundreds[0]=Tens[3];

Tens=Tens<<1;
Tens[0]=Ones[3];

Ones=Ones<<1;
Ones[0]=binary[i];
end
end
endmodule

// Hex to 7 Segment Example
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//----------------------------------------- 
module hexto7segment(hex , seg);
    input  [3:0] hex;
    output [7:0] seg;
    reg    [7:0] seg;
    
        
 // segment encoding
 //      0
 //     ---  
 //  5 |   | 1
 //     ---   <- 6
 //  4 |   | 2
 //     ---
 //      3
 always @(hex)
 begin
  case (hex)
       // Dot point is always disable
       4'b0001 : seg = 8'b11111001;   //1 = F9H
       4'b0010 : seg = 8'b10100100;   //2 = A4H
       4'b0011 : seg = 8'b10110000;   //3 = B0H
       4'b0100 : seg = 8'b10011001;   //4 = 99H
       4'b0101 : seg = 8'b10010010;   //5 = 92H
       4'b0110 : seg = 8'b10000010;   //6 = 82H
       4'b0111 : seg = 8'b11111000;   //7 = F8H
       4'b1000 : seg = 8'b10000000;   //8 = 80H
       4'b1001 : seg = 8'b10010000;   //9 = 90H
       4'b1010 : seg = 8'b10001000;   //A = 88H
       4'b1011 : seg = 8'b10000011;   //b = 83H
       4'b1100 : seg = 8'b11000110;   //C = C6H
       4'b1101 : seg = 8'b10100001;   //d = A1H
       4'b1110 : seg = 8'b10000110;   //E = 86H
       4'b1111 : seg = 8'b10001110;   //F = 8EH
       default : seg = 8'b11000000;   //0 = C0H
     endcase
   end
   
endmodule