使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計BCD to Binary 為例(FPGA開發平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計BCD to Binary 為例(FPGA開發平台)

9999 =0b10011100001111

BCD numbers are representations of decimal (base 10) numbers, and like all modern number systems, BCD numbers use positional weighting. Each BCD digit in a given number contributes a magnitude equal to the digit multiplied by its weight, and each digit’s weight is equal to 10 raised to the power of the digit’s position in the number. Consider the BCD number 987, stored as three 4-bit BCD codes: 1001 for 9 (digit 2), 1000 for 8 (digit 1), and 0111 for 7 (digit 0). To find the binary equivalent, each BCD digit is multiplied by its weighted magnitude: 9 x 10^2 + 8 * 10^1 + 7 * 10^0, or 9 * 100 + 8 * 10+ 7 * 1. The Verilog code below illustrates converting a 4-digit BCD number to it’s binary equivalent.

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );
 input  [17:0] SW;   // toggle switches
 input  [7:0] KEY;       // Push bottom
 input  CLOCK_50;   //Clock 27MHz , 50Mhz
 output [17:0] LEDR;   // red  LEDS
 output [8:0] LEDG;   // green LEDs
 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
 output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
 inout  [35:0] GPIO;
 assign HEX0=7'b111_1111;
 assign HEX1=7'b111_1111;
 assign HEX2=7'b111_1111;
 assign HEX3=7'b111_1111;
 assign HEX4=7'b111_1111;
 assign HEX5=7'b111_1111;
 assign HEX6=7'b111_1111;
 assign HEX7=7'b111_1111;
 
//module bcd2bin
//    input wire [3:0] bcd3, 
//    input wire [3:0] bcd2, 
//    input wire [3:0] bcd1, 
//    input wire [3:0] bcd0, 
//    output wire [13:0] bin
bcd2bin(SW[15:12],SW[11:8],SW[7:4],SW[3:0],LEDR[13:0]);
endmodule

module bcd2bin
   (
    input wire [3:0] bcd3, 
    input wire [3:0] bcd2, 
    input wire [3:0] bcd1, 
    input wire [3:0] bcd0, 
    output wire [13:0] bin
   );
   assign bin = (bcd3 * 10'd1000) + (bcd2*7'd100) + (bcd1*4'd10) + bcd0;
endmodule

/*
module bin2bcd(
   input [13:0] bin,
   output reg [15:0] bcd
   );
   
integer i;

always @(bin) begin
    bcd=0;
    for (i=0;i<14;i=i+1) begin //Iterate once for each bit in input number
        if (bcd[3:0] >= 5) bcd[3:0] = bcd[3:0] + 3; //If any BCD digit is >= 5, add three
if (bcd[7:4] >= 5) bcd[7:4] = bcd[7:4] + 3;
if (bcd[11:8] >= 5) bcd[11:8] = bcd[11:8] + 3;
if (bcd[15:12] >= 5) bcd[15:12] = bcd[15:12] + 3;
bcd = {bcd[14:0],bin[13-i]}; //Shift one bit, and shift in proper bit from input 
    end
end
endmodule
*/