使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計 14 bit Binary to BCD 為例(FPGA開發平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計 14bits Binary to BCD 為例(FPGA開發平台)

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );

 input  [17:0] SW;   // toggle switches
 input  [7:0] KEY;       // Push bottom
 input  CLOCK_50;   //Clock 27MHz , 50Mhz
 output [17:0] LEDR;   // red  LEDS
 output [8:0] LEDG;   // green LEDs
 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
 output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
 inout  [35:0] GPIO;
 //assign HEX0=7'b111_1111;
 //assign HEX1=7'b111_1111;
 //assign HEX2=7'b111_1111;
 //assign HEX3=7'b111_1111;
 //assign HEX4=7'b111_1111;
 assign HEX5=7'b111_1111;
 assign HEX6=7'b111_1111;
 assign HEX7=7'b111_1111;
 
 wire [17:0]bcd_out;
 assign LEDR[17:0]=bcd_out;
 wire [7:0] segout0;   //HEX 0
 wire [7:0] segout1;   //HEX 1
 wire [7:0] segout2;   //HEX 2
 wire [7:0] segout3;   //HEX 3
 wire [7:0] segout4;   //HEX 4
 //bin2bcd(
 //  input [13:0] bin,
 //  output reg [15:0] bcd
 bin2bcd(SW[13:0],bcd_out);
 
 _7seg UUT0(.hex((bcd_out[3:0]))  , .seg(segout0));
 _7seg UUT1(.hex((bcd_out[7:4]))  , .seg(segout1));
 _7seg UUT2(.hex((bcd_out[11:8])) , .seg(segout2));
 _7seg UUT3(.hex((bcd_out[15:12])), .seg(segout3));
 _7seg UUT4(.hex({2'b00,bcd_out[17:16]}), .seg(segout4));
 
 assign HEX0=segout0[6:0];
 assign HEX1=segout1[6:0];
 assign HEX2=segout2[6:0];
 assign HEX3=segout3[6:0];
 assign HEX4=segout4[6:0];
endmodule

//Binary to BCD
module bin2bcd(
   input [13:0] bin,
   output reg [17:0] bcd
   );
   
integer i;

always @(bin) begin
    bcd=0;
    for (i=0;i<14;i=i+1) begin //Iterate once for each bit in input number
        if (bcd[3:0] >= 5) bcd[3:0] = bcd[3:0] + 3; //If any BCD digit is >= 5, add three
if (bcd[7:4] >= 5)    bcd[7:4] = bcd[7:4] + 3;
if (bcd[11:8] >= 5) bcd[11:8] = bcd[11:8] + 3;
if (bcd[15:12] >= 5) bcd[15:12] = bcd[15:12] + 3;
//if (bcd[17:16] >= 5) bcd[17:16] = bcd[17:16] + 3;
bcd = {bcd[17:0],bin[13-i]}; //Shift one bit, and shift in proper bit from input 
    end
end
endmodule