使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計JK Flip-Flop (edge-triggered)為例(Test Bench平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計JK Flip-Flop (edge-triggered)為例(Test Bench平台) 

module jk_FF_edge_triggered(Q, Qn, C, J, K, RESETn);

   output Q;
   output Qn;
   input  C;
   input  J;
   input  K;
   input  RESETn;
   wire   Kn;   // The complement of the K input.
   wire   D;   
   wire   D1;   // Data input to the D latch.   
   wire   Cn;   // Control input to the D latch.
   wire   Cnn;  // Control input to the SR latch.
   wire   DQ;   // Output from the D latch, inputs to the gated SR latch (S).
   wire   DQn;  // Output from the D latch, inputs to the gated SR latch (R).
   assign D1 = !RESETn ? 0 : D;  // Upon reset force D1 = 0
   not(Kn, K);   
   and(J1, J, Qn);
   and(K1, Kn, Q);   
   or(D, J1, K1);   
   not(Cn, C);
   not(Cnn, Cn);   
   d_latch dl(DQ, DQn, Cn, D1);
   sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);   
endmodule // jk_flip_flop_edge_triggered
module d_latch(Q, Qn, G, D);
   output Q;
   output Qn;
   input  G;   
   input  D;
   wire   Dn; 
   wire   D1;
   wire   Dn1;
   not(Dn, D);   
   and(D1, G, D);
   and(Dn1, G, Dn);   
   nor(Qn, D1, Q);
   nor(Q, Dn1, Qn);
endmodule // d_latch
module sr_latch_gated(Q, Qn, G, S, R);
   output Q;
   output Qn;
   input  G;   
   input  S;
   input  R;
   wire   S1;
   wire   R1;
   
   and(S1, G, S);
   and(R1, G, R);   
   nor(Qn, S1, Q);
   nor(Q, R1, Qn);
endmodule // sr_latch_gated

`timescale 10ns/10ps
module tb_jk_FF_edge_triggered;
reg tCLK;
reg tJ;
reg tK;
reg tRESETn;
wire tQ, tQn;
//module jk_FF_edge_triggered(Q, Qn, C, J, K, RESETn);
jk_FF_edge_triggered  DUT(tQ, tQn, tCLK, tJ, tK, tRESETn);
//instantiate counter to be tested.
initial
begin
#0  tCLK=1'b0; //tCLK;
#0  tRESETn=1'b1; //tRESETn=1'b0
#5  tRESETn=1'b0; //tRESETn=1’b1;
#10 tRESETn=1'b1; //tRESETn=1'b0
#12 tJ=1'b1;tK=1'b1;
#22 tJ=1'b0;tK=1'b1;
#32 tJ=1'b1;tK=1'b1;
#42 tJ=1'b1;tK=1'b0;
#52 tJ=1'b0;tK=1'b0;
#62 tJ=1'b0;tK=1'b1;
#72 tJ=1'b1;tK=1'b1;
#82 tJ=1'b1;tK=1'b1;

#100 $stop;
end
always begin
#10 tCLK=~tCLK; //generate clock
end       
endmodule