P6-6-2 計數器的基礎 適用於DE2-70
reg [3:0] Count_inc
reg [3:0] Count_dec
always @ (posedge CLOCK_50)
begin
Count_inc = Count_inc + 4'b1;
Count_dec = Count_dec - 4'b1;
end
module Dff_KEYdelay(CLOCK_50,KEY,LEDG);
input CLOCK_50; //Clock 50MHZ
input [3:0] KEY;
output reg [7:0] LEDG;
reg [3:0] key_delay0;
reg [3:0] key_delay1;
reg [27:0] Counter_inc ;
always @ (posedge CLOCK_50)
begin
if (!key_delay0[3] && key_delay0[2]) //KEY[0] = Counter_inc[27]
LEDG[0]<= ~LEDG[0];
if (!key_delay1[3] && key_delay1[2]) //KEY[1] = Counter_inc[25]
LEDG[7:1]<= LEDG[6:0]; //Shift left
key_delay0 <= { key_delay0[2:0],Counter_inc[27]}; //delay for KEY[0]
key_delay1 <= { key_delay1[2:0],Counter_inc[25]}; //delay for KEY[1]
Counter_inc = Counter_inc + 28'b1;
end
endmodule


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