module top_module (CLOCK_50,SW, KEY, LEDR, LEDG );
input [17:0] SW; // toggle switches
input [7:0] KEY;
input CLOCK_50; //Clock 50MHZ
output [17:0] LEDR; // red LEDs
output [7:0] LEDG; // green LEDs
/* ( CLK, RSTn, LED_Out); */
wire RSTn;
wire CLK;
wire [3:0]LED_Out;
assign RSTn=KEY[0];
assign CLK=CLOCK_50;
/*******************************/
wire LED0_Out;
led0_module U1
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( LED0_Out )
);
/*********************************/
wire LED1_Out;
led1_module U2
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( LED1_Out )
);
/*********************************/
wire LED2_Out;
led2_module U3
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( LED2_Out )
);
/*********************************/
wire LED3_Out;
led3_module U4
(
.CLK( CLK ),
.RSTn( RSTn ),
.LED_Out( LED3_Out )
);
/**********************************/
assign LED_Out = { LED3_Out, LED2_Out, LED1_Out, LED0_Out};
assign LEDG[3:0]=LED_Out;
/***********************************/
endmodule
//*******************************************************
module led0_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
/*************************************/
parameter T10MS = 21'd2_000_000;
/*************************************/
reg [20:0]Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 21'd0;
else if( Count1 == T10MS )
Count1 <= 21'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 21'd0 && Count1 < 21'd500_000 )
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
//************************************************************
module led1_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
/*************************************/
parameter T10MS = 21'd2_000_000;
/*************************************/
reg [20:0]Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 21'd0;
else if( Count1 == T10MS )
Count1 <= 21'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 21'd500_000 && Count1 < 21'd1_000_000 )
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
//*********************************************************************
module led2_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
/*************************************/
parameter T10MS = 21'd2_000_000;
/*************************************/
reg [20:0]Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 21'd0;
else if( Count1 == T10MS )
Count1 <= 21'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 21'd1_000_000 && Count1 < 21'd1_500_000 )
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
//*******************************************************************
module led3_module
(
CLK, RSTn, LED_Out
);
input CLK;
input RSTn;
output LED_Out;
/*************************************/
parameter T10MS = 21'd2_000_000;
/*************************************/
reg [20:0]Count1;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
Count1 <= 21'd0;
else if( Count1 == T10MS )
Count1 <= 21'd0;
else
Count1 <= Count1 + 1'b1;
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 21'd1_500_000 && Count1 < 21'd2_000_000 )
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
/***************************************/
assign LED_Out = rLED_Out;
/***************************************/
endmodule
//**************************************************************
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