LAB03 KEY Debounce

LAB03 KEY debounce 適用於DE2-70
//RESET ==> KEY[0]
//Pin_IN ==> KEY[1]
//Pin_out ==> LEDG[0]

module debounce_module(CLOCK_27,SW, KEY, LEDR, LEDG );

input  [17:0] SW; // toggle switches
input  [7:0]  KEY;
input  CLOCK_27;    //Clock 27MHZ
output [17:0] LEDR; // red LEDs
output [7:0]  LEDG; // green LEDs


   // (CLK, RSTn, Pin_In, Pin_Out);
    
wire CLK;
wire RSTn;
wire Pin_In;
wire Pin_Out;


assign CLK=CLOCK_27;
assign RSTn=KEY[0];
assign Pin_In=KEY[1];
assign LEDG[0]=Pin_Out;

 
/**************************/
 
wire H2L_Sig;
wire L2H_Sig;
 
detect_module U1
(
    .CLK( CLK ),
 .RSTn( RSTn ),
 .Pin_In( Pin_In ),   // input - from top
 .H2L_Sig( H2L_Sig ), // output - to U2
 .L2H_Sig( L2H_Sig )  // output - to U2
);
 
/**************************/
 
delay_module U2
(
    .CLK( CLK ),
 .RSTn( RSTn ),
 .H2L_Sig( H2L_Sig ), // input - from U1
 .L2H_Sig( L2H_Sig ), // input - from U1
 .Pin_Out( Pin_Out )  // output - to top
);
 
/*******************************/

endmodule





module detect_module 
(
    CLK, RSTn, Pin_In, H2L_Sig, L2H_Sig
);

    input CLK;
input RSTn;
input Pin_In;
output H2L_Sig;
output L2H_Sig;
 
/**********************************/
 
parameter T100US = 11'd1999;
 
/**********************************/
 
reg [10:0]Count1;
reg isEn;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     begin
         Count1 <= 11'd0;
         isEn <= 1'b0;
end
    else if( Count1 == T100US )
isEn <= 1'b1;
 else
     Count1 <= Count1 + 1'b1;

    /********************************************/
 
reg H2L_F1;
reg H2L_F2;
reg L2H_F1;
reg L2H_F2;
 
always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     begin
   H2L_F1 <= 1'b1;
H2L_F2 <= 1'b1;
L2H_F1 <= 1'b0;
L2H_F2 <= 1'b0;
  end
 else
     begin
H2L_F1 <= Pin_In; 
H2L_F2 <= H2L_F1;
L2H_F1 <= Pin_In;
L2H_F2 <= L2H_F1;
end

    /***********************************/
 

assign H2L_Sig = isEn ? ( H2L_F2 & !H2L_F1 ) : 1'b0;
assign L2H_Sig = isEn ? ( !L2H_F2 & L2H_F1 ) : 1'b0;

 
/***********************************/
 
endmodule

    
 


module delay_module 
(
    CLK, RSTn, H2L_Sig, L2H_Sig, Pin_Out
);

    input CLK;
input RSTn;
input H2L_Sig;
input L2H_Sig;
output Pin_Out;
 
/****************************************/
 
parameter T1MS = 16'd19_999;
 
/***************************************/
 
reg [15:0]Count1;

always @ ( posedge CLK or negedge RSTn )
    if( !RSTn )
     Count1 <= 16'd0;
 else if( isCount && Count1 == T1MS )
     Count1 <= 16'd0;
 else if( isCount )
     Count1 <= Count1 + 1'b1;
 else if( !isCount )
     Count1 <= 16'd0;

    /****************************************/

    reg [3:0]Count_MS;
   
always @ ( posedge CLK or negedge RSTn )
        if( !RSTn )
     Count_MS <= 4'd0;
 else if( isCount && Count1 == T1MS )
     Count_MS <= Count_MS + 1'b1;
 else if( !isCount )
     Count_MS <= 4'd0;

/******************************************/

reg isCount;
reg rPin_Out;
reg [1:0]i;

always @ ( posedge CLK or negedge RSTn )
   if( !RSTn )
    begin
        isCount <= 1'b0;
rPin_Out <= 1'b0;
i <= 2'd0;
 end
else
     case ( i )

   2'd0 : 
if( H2L_Sig ) i <= 2'd1;
else if( L2H_Sig ) i <= 2'd2;

   2'd1 : 
if( Count_MS == 4'd10 ) begin isCount <= 1'b0; rPin_Out <= 1'b1; i <= 2'd0; end
   else isCount <= 1'b1;
 
2'd2 :
if( Count_MS == 4'd10 ) begin isCount <= 1'b0; rPin_Out <= 1'b0; i <= 2'd0; end
   else isCount <= 1'b1;
  

endcase

    /********************************************/
 
assign Pin_Out = rPin_Out;
 
/********************************************/
     


endmodule