"=" 區塊指定 Blocking assignment
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always @ (posedge Clk)
begin
Q1=W;
Q2=Q1;
end
endmoudle
"<=" 非區塊指定 nonBlocking assignment
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always @ (posedge Clk)
begin
Q1<=W;
Q2<=Q1;
end
endmoudle
區塊指定 Blocking assignment
10 module d_latch2 (
11 input rst_n,
12 input en,
13 input d,
14 output reg q
15 );
16
17 always@(rst_n, en, d, q) begin
18 if (!rst_n)
19 q = 0;
20 else if (en)
21 q = d;
22 end
23
24 endmodule
非區塊指定 nonBlocking assignment
10 module d_ff (
11 input clk,
12 input rst_n,
13 input en,
14 input d,
15 output reg q
16 );
17
18 always@(posedge clk or negedge rst_n)
19 if (!rst_n)
20 q <= 0;
21 else if (en)
22 q <= d;
23
24 endmodule
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