結果顯示於 7-seg Display HEX0---HEX4
255x255 =65025
參考http://ccckmit.wikidot.com/ve:multiplier
module multiplier(a,b, ab);
input [3:0] a,b;
output [7:0] ab;
wire [3:0] t0,t1,t2,t3;
assign t0 = (b[0]==1) ? a : 4'h0;
assign t1 = (b[1]==1) ? a : 4'h0;
assign t2 = (b[2]==1) ? a : 4'h0;
assign t3 = (b[3]==1) ? a : 4'h0;
assign ab=t0+(t1<<1)+(t2<<2)+(t3<<3);
endmodule
//===============================================================
module ex2(SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 );
input [17:0] SW; // toggle switches
input [3:0] KEY; // Push bottom
input CLOCK_27; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3 ,HEX4; //7-segment display
wire [7:0] segout0; //HEX 0
wire [7:0] segout1; //HEX 1
wire [7:0] segout2; //HEX 2
wire [7:0] segout3; //HEX 3
wire [7:0] segout4; //HEX 4
reg [3:0] ten_thousand_t;
reg [3:0] thousand_t;
reg [3:0] hundred_t;
reg [3:0] tens_t;
reg [3:0] ones_t;
//set original program input , output
//(a,b, ab);
//input [7:0] a,b;
//output [15:0] ab;
wire [7:0] a,b;
reg [15:0] ab;
assign a=SW[7:0];
assign b=SW[15:8];
assign LEDR=SW[15:0];
reg [7:0] t0,t1,t2,t3;
reg [7:0] t4,t5,t6,t7;
always @(a or b)
begin
t0 <= (b[0]==1) ? a : 4'h0;
t1 <= (b[1]==1) ? a : 4'h0;
t2 <= (b[2]==1) ? a : 4'h0;
t3 <= (b[3]==1) ? a : 4'h0;
t4 <= (b[4]==1) ? a : 4'h0;
t5 <= (b[5]==1) ? a : 4'h0;
t6 <= (b[6]==1) ? a : 4'h0;
t7 <= (b[7]==1) ? a : 4'h0;
ab <= (t0+(t1<<1)+(t2<<2)+(t3<<3)+(t4<<4)+(t5<<5)+(t6<<6)+(t7<<7));
end
// module _16bit_BIN2BCD(Binary ,ones ,tens , hundred, thousand, ten_thousand);
_16bit_BIN2BCD (ab,ones_t,tens_t,hundred_t,thousand_t,ten_thousand_t);
_7seg UUT0(.hex(ones_t),
.seg(segout0));
_7seg UUT1(.hex(tens_t),
.seg(segout1));
_7seg UUT2(.hex(hundred_t),
.seg(segout2));
_7seg UUT3(.hex(thousand_t),
.seg(segout3));
_7seg UUT4(.hex(ten_thousand_t),
.seg(segout4));
assign HEX0=segout0[6:0];
assign HEX1=segout1[6:0];
assign HEX2=segout2[6:0];
assign HEX3=segout3[6:0];
assign HEX4=segout4[6:0];
task _16bit_BIN2BCD;
//(Binary,ones,tens, hundred, thousand, ten_thousand);
/*
Algorithm:
If any column (10000'S, 1000'S ,100's, 10's, 1's, etc.) is 5 or greater, add 3 to that column.
Shift all #'s to the left 1 position.
If 8 shifts have been performed, it's done! Evaluate each column for the BCD values.
Go to step 1.
*/
input [15:0] Binary ;
output [3:0] ones;
output [3:0] tens;
output [3:0] hundred;
output [3:0] thousand;
output [3:0] ten_thousand;
reg [3:0] ones;
reg [3:0] tens;
reg [3:0] hundred;
reg [3:0] thousand;
reg [3:0] ten_thousand;
integer i;
// always @ (Binary)
begin
//set 4'd0
ten_thousand=4'd0;
thousand=4'd0;
hundred=4'd0;
tens=4'd0;
ones=4'd0;
for (i=15;i>=0;i=i-1)
begin
if (ten_thousand>=5)
ten_thousand = ten_thousand +3;
if (thousand>=5)
thousand = thousand +3;
if (hundred>=5)
hundred = hundred +3;
if (tens>=5)
tens = tens +3;
if (ones>=5)
ones = ones +3;
// shift left 1 bit
ten_thousand = ten_thousand <<1;
ten_thousand[0]= thousand[3];
thousand = thousand <<1;
thousand[0]= hundred[3];
hundred = hundred <<1;
hundred[0]= tens[3];
tens = tens<<1;
tens[0]= ones[3];
ones = ones<<1;
ones[0]= Binary[i];
end
end
endtask
endmodule
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
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