P6-10 D Flip-Flop 同步及非同步Reset 電路

P6-10  D Flip-Flop 同步及非同步Reset  電路

//同步Reset  
module (nRst,D,Clk,Q);
  input nRst,D,Clk;
  output Q;
  //同步Reset 
  always @(posedge Clk)
    if (!nRst)
      Q<=1'b0;
    else
      Q<=D;
endmodule

//非同步Reset  電路

module (nRst,D,Clk,Q);
  input nRst,D,Clk;
  output Q;
  //非同步Reset 
  always @(posedge Clk or negedge nRst)
    if (!nRst)
      Q<=1'b0;
    else
      Q<=D;
endmodule



源自於http://eesun.free.fr/DOC/VERILOG/synvlg.html


D Type Flip Flops:
Two things to note about inferring flip flops:

• Non blocking signal assignment (<=) should always be used
• The sensitivity list must have the keyword posedge or negedge. (also for resets)

D-type flip flop reg q; always @ (posedge clk)   q <= d;

 非同步Reset  電路

D type flip flop with asynchronous reset reg q; always @ (posedge clk or posedge reset)   if (reset)     q <= 1'b0;   else     q <= d;

  同步Reset  電路

D type flip flop with synchronous reset reg q; always @ (posedge clk)   if (reset)     q <= 1'b0;   else     q <= d;

  

D type flip flop with gated clock reg q; wire gtd_clk = enable && clk; always @ (posedge gtd_clk)   q <= d;

  

Data enbled D type flip flop reg q; always @ (posedge clk)   if (enable)     q <= d;

  
  

Negative edge triggered D type flip flop reg q; always @ (negedge clk)   q <= d;

Latches

Latch reg q; always @ (q or enable)    if (enable)       q = d;