LAB10 BCD substrator (BCD減法器) 適用於DE2-70
a - b - bor_in = {bor_out , diff_10out, diff_out}
0-0-0=0 , 9-0-0=9 , 0-9-1=-10
SW[17] 前一級借位 輸入
SW[7:4] 被減數 輸入
SW[3:0] 減數 輸入
HEX1-HEX0 差 輸出
LEDG[0] 借位 輸出
//------------------------------------
//4-bit BCD substrator
//Filename : BCD_substrator.v
//------------------------------------
module BCD_Substrator(SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 );
input [17:0] SW; // toggle switches
input [7:0] KEY; // Push bottom
input CLOCK_27; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
//(Diff , Bor_out, Bor_in, A, B);
//output Diff [3:0] S; //Difference output
//output Bor_out; //Borrow out
//input Bor_in; //Borrow in
//input [3:0] A, B; //Input data minuend / subtrahend A-B
// A-B-Bor_in = Diff , Bor_out
wire Bor_in; //Borrow in
wire [3:0] A,B; //Input data minuend / subtrahend A-B
reg [3:0] Diff_out; //Difference output
reg [3:0] Diff_10out;
wire Bor_out; //Carry out
wire [7:0] segout0; //HEX 0
wire [7:0] segout1; //HEX 1
assign A=SW[7:4] ; //minuend A
assign B=SW[3:0] ; //subtrahend B
assign Bor_in=SW[17]; //Borrow in Bor_in
assign LEDR[7:0]=SW[7:0];
assign LEDR[17]=SW[17];
reg [3:0] A_tmp,B_tmp1;
wire [3:0] S_tmp,B_tmp,Diff_tmp;
wire C4;
reg [3:0] A_mod,B_mod;
//debug
//wire [3:0] B_tmp2;
always @ ( A or B or Bor_in )
begin
if (A<10)
A_tmp = A; //若是>9 則為9
else
A_tmp =4'b1001;
if (B<10)
B_tmp1 = B; //若是>9 則為9
else
B_tmp1 =4'b1001;
end
_9s_complement(.Xin(B_tmp1), .Xout(B_tmp));
BCD_4bit_FA U1( .S1(S_tmp),
.Cout1(C4),
.Cin1(1'b0),
.A1(A_tmp),
.B1(B_tmp));
//debug
//assign LEDR[15:12]=S_tmp;
//assign LEDR[16]=C4;
always @ ( A_tmp or B_tmp or C4 or S_tmp or Bor_in)
begin
case (C4)
0 : begin
B_mod = ~S_tmp; //Modified code
A_mod = 4'b1010;
end
1: begin
B_mod = S_tmp;
A_mod = 4'b0000;
end
endcase
end
adder4 U2 ( .S(Diff_tmp),
.Cout(),
.A(A_mod),
.B(B_mod),
.Cin(C4));
always @ ( A_mod or B_mod or Diff_tmp or Bor_in)
begin
Diff_10out=4'b0; //前一級借位的處理
case (Bor_in) //Process Borrow in
0:
Diff_out=Diff_tmp; //前一級借位=0
1: begin // Diff_out <0 //前一級借位=1
if (Bor_out)
Diff_out= Diff_tmp + 4'b1; //結果<0 , 負號
else
Diff_out= Diff_tmp + 4'b1111; //結果>0 , 正號
if (Diff_out==4'b1111) // 結果=0 0-1=0xf , 變成-1
Diff_out=4'b1;
if (Diff_out==4'b1010) // A=1010 ==>0001 0000 變成- 10
begin
Diff_10out=4'b1;
Diff_out=4'b0;
end
else
Diff_10out=4'b0;
end
default:
Diff_out=Diff_tmp;
endcase
end
/*
always @ ( C4)
begin
if (~C4)
segout1[6:0]=7'b011_1111; //minus
else
segout1[6:0]=7'b111_1111;
end
assign HEX1=segout1[6:0];
*/
assign Bor_out = ~C4;
assign LEDG[0]=Bor_out;
_7seg UUT0(.hex((Diff_out)),
.seg(segout0));
assign HEX0=segout0[6:0];
_7seg UUT1(.hex({3'b0,Diff_10out}),
.seg(segout1));
assign HEX1=segout1[6:0];
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
endmodule
//----------------------
//4-bit unsigned adder
//Filename : adder4.v
//----------------------
module adder4(S, Cout, A, B, Cin);
output [3:0] S; //4-bit sum
output Cout; //Carry out
input [3:0] A, B; //Inputs
input Cin; //Carry in
//Assign the sum of (A+B+Cin) to Cout and Sum
assign {Cout, S} = A + B + Cin;
endmodule
//----------------------
//
//Filename : nine's complement
//----------------------
module _9s_complement(Xin, Xout);
output [3:0] Xout; //4-bit 9's complement
input [3:0] Xin; //Inputs
//Assign the 9's complement Xout = Xin + 1010 ;
assign Xout = ~Xin + 4'b1010 ;
/*adder4(.S(Xout),
.Cout(),
.A(~Xin),
.B(4'b1010),
.Cin(1'b0)
); */
endmodule
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
module BCD_4bit_FA ( S1, Cout1, Cin1, A1, B1);
output [3:0] S1; //Sumation output
output Cout1; //Carry out
input Cin1; //Carry in
input [3:0] A1, B1;//Input data
wire [3:0] A_tmp11,B_tmp11,S_tmp11;
wire C41;
reg [3:0] B_mod11;
reg F1;
//4-bit binary adder
adder4 BINADD(
.S(S_tmp11),
.Cout(C41),
.Cin(Cin1),
.A(A1),
.B(B1)
);
//Modify binary code with '0110'
adder4 MODADD(
.S(S1),
.Cout(),
.Cin(1'b0),
.A(S_tmp11),
.B(B_mod11)
);
always @ (Cin1 or A1 or B1 or C41 or S_tmp11)
begin
//F=C4+S3(S2+S1)
F1 = (C41 | (S_tmp11[3] & (S_tmp11[2] | S_tmp11[1])));
B_mod11 = {1'b0, F1, F1, 1'b0}; //Modified code
end
assign Cout1 = F1;
endmodule
Binary Logic: Basic Boolean Operators (AND, OR, NOT).
