以Verilog 設計一個數位電路 (2)---and , not 邏輯閘

以Verilog 設計一個數位電路 (2)---and , not 邏輯閘

自動產生的verilog 程式
module block1(
in1,
in2,
out1
);


input in1;
input in2;
output out1;

wire SYNTHESIZED_WIRE_0;
assign SYNTHESIZED_WIRE_0 =  ~in1;
assign out1 = SYNTHESIZED_WIRE_0 & in2;

endmodule


程式與測試平台程式

`timescale 1 ns/1 ns

module EX_102 (in1, in2, out1);
input  in1, in2;
output out1;
wire   in1, in2;
wire   out1;

assign out1 = ~in1 & in2;


endmodule


//=============================
//測試平台
//=============================
`timescale 100 ns/1 ns

module testbench;
reg in1, in2;
wire out1;

EX_102 UUT(
.in1(in1),
.in2(in2),
.out1(out1) );
initial
begin
 in1  = 1'b0; // Time = 0
 in2  = 1'b0;

 #50; // Time = 50
 in2  = 1'b0; in1  = 1'b1;

 #50; // Time = 100
 in2  = 1'b1; in1  = 1'b0;

 #50; // Time = 150
 in2  = 1'b1; in1  = 1'b1;

 #50;
 $stop;

end

endmodule