以Verilog 設計一個數位電路 (EX1-3)--- 74LS154

以Verilog 設計一個數位電路 (EX1-3)--- 74LS154

`timescale 1 ns/1 ns
module ex3_74LS154 ( A,B,C,D,E1,E2,Y );
input A,B,C,D,E1,E2;
output  [15:0]Y;


assign Y[0]  = ~ ( ~E1 & ~E2 & (~A & ~B & ~C & ~D )) ;
assign Y[1]  = ~ ( ~E1 & ~E2 & (~A & ~B & ~C &  D )) ;
assign Y[2]  = ~ ( ~E1 & ~E2 & (~A & ~B &  C & ~D )) ;
assign Y[3]  = ~ ( ~E1 & ~E2 & (~A & ~B &  C &  D )) ;
assign Y[4]  = ~ ( ~E1 & ~E2 & (~A &  B & ~C & ~D )) ;
assign Y[5]  = ~ ( ~E1 & ~E2 & (~A &  B & ~C &  D )) ;
assign Y[6]  = ~ ( ~E1 & ~E2 & (~A &  B &  C & ~D )) ;
assign Y[7]  = ~ ( ~E1 & ~E2 & (~A &  B &  C &  D )) ;

assign Y[8]   = ~ ( ~E1 & ~E2 & ( A & ~B & ~C & ~D )) ;
assign Y[9]   = ~ ( ~E1 & ~E2 & ( A & ~B & ~C &  D )) ;
assign Y[10]  = ~ ( ~E1 & ~E2 & ( A & ~B &  C & ~D )) ;
assign Y[11]  = ~ ( ~E1 & ~E2 & ( A & ~B &  C &  D )) ;
assign Y[12]  = ~ ( ~E1 & ~E2 & ( A &  B & ~C & ~D )) ;
assign Y[13]  = ~ ( ~E1 & ~E2 & ( A &  B & ~C &  D )) ;
assign Y[14]  = ~ ( ~E1 & ~E2 & ( A &  B &  C & ~D )) ;
assign Y[15]  = ~ ( ~E1 & ~E2 & ( A &  B &  C &  D )) ;
   
endmodule

`timescale 100 ns/1 ns

module testbench;

/*

module ex3_74LS154 ( A,B,C,D,E1,E2 ,Y );

input A,B,C,D,E1,E2;

output  [15:0Y;

*/

reg  A,B,C,D,E1,E2;

wire [15:0]Y;

integer i;

ex3_74LS154 UUT ( A,B,C,D,E1,E2 ,Y );

initial

begin

for (i=0;i<=63;i=i+1) begin

{E1,E2,A,B,C,D}=i;

#10;

end

#10;  

$stop;

end

endmodule