Verilog Code for OR Gate – All modeling styles

Verilog Code for OR Gate – All modeling styles

Gate Level modeling

module OR_2_gate_level(output Y, input A, B);
   or(Y, A, B); 
endmodule

Data flow modeling

module OR_2_data_flow (output Y, input A, B);

assign Y = A | B; 
endmodule

Behavioral Modeling

Truth Table for OR gate

A	B	Y(A or B)
0	0	0
0	1	1
1	0	1
1	1	1

Equation from the truth table

Y = A + B or say Y = A or B.

module OR_2_behavioral (output reg Y, input A, B);
always @ (A or B) begin
    if (A == 1'b0 & B == 1'b0) begin
        Y = 1'b0;
    end
    else 
        Y = 1'b1; 
end
endmodule

RTL schematic of OR gate

Testbench of the OR gate using Verilog

`include "OR_2_behavioral.v"

`timescale 100ns/1ns
module OR_2_behavioral_tb;
reg A, B;
wire Y;
OR_2_behavioral Indtance0 (Y, A, B);
initial begin
    A = 0; B = 0;
 #1 A = 0; B = 1;
 #1 A = 1; B = 0;
 #1 A = 1; B = 1;   
end
initial begin
    $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
    $dumpfile("dump.vcd");
    $dumpvars();
end
endmodule