以Verilog 設計一個數位電路 (EX_201)--- always行為模式 --and 電路

以Verilog 設計一個數位電路 (EX_201)--- always行為模式 --and 電路

`timescale 1 ns/1 ns

module EX_201 (a, b, c, d, e);
input  a, b, c;
output d, e;
reg    d, e;

// non-behavioral writing style is also listed for comparison.
// d and e should be declared as wire in non-behavioral
// writing style.
//
// wire d, e;
//
// assign d = a & b;
// assign e = b & c;

always@(a or b or c)
begin
d = a & b;
e = b & c;
end

endmodule

`timescale 100 ns/1 ns

module testbench;

reg a, b, c;

wire d, e;

integer i;

EX_201 UUT(

.a(a),

.b(b),

.c(c),

.d(d),

.e(e) );

initial

begin

 for (i=0;i<=7;i=i+1) begin

{a,b,c}=i;

#20;

 end

 #20;

 $stop;

end

endmodule