以Verilog 設計一個數位電路 (12)--- Shift Rotate

以Verilog 設計一個數位電路 (12)--- Shift  Rotate

`timescale 1 ns/1 ns

module EX_112 (a, b, c, d);
input [7:0] a;
output [7:0] b, c, d;
wire [7:0] b, c, d;

assign b = { a[6:0], a[7] };

assign c = { a[0], a[7:1] };

assign d = { a[3:0], a[7:4] };


endmodule

`timescale 100 ns/1 ns

module testbench;

reg [7:0] a;

wire [7:0] b, c, d;

EX_112 UUT (

.a(a),

.b(b),

.c(c),

.d(d) );

initial

begin

 a   = 8'h0f; // Time = 0

 #50; // Time = 50

 a   = 8'h5a;

 #50

  $stop;

end

endmodule