Verilog Types of Nets

A net data type must be used when a signal is:

• driven by the output of some devices.
• declared as an input or inout port.
• on the left-hand side of a continuous assignment statement.

Types of Nets

Wire

The keyword wire is the most commonly used net in modeling circuits. When used in the code, it exhibits the same property as an electrical wire used for making connections.

module and_gate;

input wire A,B;
output wire C;

assign C = A & B;

endmodule

Tri

This is another type of net that has identical syntax and function as wire.

module 2:1_mux(out, a,b, control);

output out;
input a,b,control;
tri out;
wire a,b,control;

bufif0 b1(out, a, control); //b1 drives a when control = 0;z otherwise 
bufif1 b2(out, b, control); //b2 drives b when control = 1;z otherwise 

endmodule

bufif0(out, in, ctrl);
bufif1(out, in, ctrl);

supply0 and supply1

In every circuit we build, there are two crucial elements – power supply and ground. Hence, we use supply0 and supply1 nets to represent these two. The supply1 is used to model power supply. Whereas, the supply0 is for modeling ground.

supply1 Vcc; // all nets connected to Vcc are connected to power supply
supply0 GND; // all nets connected to GND are connected to ground