以Verilog 設計一個數位電路 (EX204)--- always --3x8_decoder電路

以Verilog 設計一個數位電路 (EX204)--- always --3x8_decoder電路 

`timescale 1 ns/1 ns

module EX_204 (a, b);
input [2:0] a;
output [7:0] b;
reg [7:0] b;

// non-behavioral writing style in EX_106 is also listed for
// comparison. b should be declared as wire in non-behavioral
// writing style.
//
// wire [7:0] b;
//
// assign b[0] = ( a==3'b000 ) ? 1'b1 : 1'b0;
// assign b[1] = ( a==3'b001 ) ? 1'b1 : 1'b0;
// assign b[2] = ( a==3'b010 ) ? 1'b1 : 1'b0;
// assign b[3] = ( a==3'b011 ) ? 1'b1 : 1'b0;
// assign b[4] = ( a==3'b100 ) ? 1'b1 : 1'b0;
// assign b[5] = ( a==3'b101 ) ? 1'b1 : 1'b0;
// assign b[6] = ( a==3'b110 ) ? 1'b1 : 1'b0;
// assign b[7] = ( a==3'b111 ) ? 1'b1 : 1'b0;

always@( a )
begin
case (a)
  3'b000  : b = 8'b0000_0001;
  3'b001  : b = 8'b0000_0010;
  3'b010  : b = 8'b0000_0100;
  3'b011  : b = 8'b0000_1000;
  3'b100  : b = 8'b0001_0000;
  3'b101  : b = 8'b0010_0000;
  3'b110  : b = 8'b0100_0000;
  default : b = 8'b1000_0000;
endcase
end

endmodule

//==========================

`timescale 100ns/1 ns

module testbench;

reg [2:0] a;

wire [7:0] b;

integer i;

EX_204 UUT(.a(a), .b(b) );

initial begin

 for (i=0;i<=7;i=i+1) begin

{a}=i;

#20;

 end

 #20;

 $stop; 

end

endmodule