Xilinx Synthesis Technology (XST)

Chapter 1 Introduction

Architecture Support 1-1

XST Flow 1-1

Chapter 2 HDL Coding Techniques

Introduction 2-2

Signed/Unsigned Support 2-13

Registers 2-13

Log File 2-14

Related Constraints 2-14

Flip-flop with Positive-Edge Clock 2-15

VHDL Code 2-15

Verilog Code 2-16

Flip-flop with Negative-Edge Clock and Asynchronous Clear 2-16

VHDL Code 2-17

Verilog Code 2-18

Flip-flop with Positive-Edge Clock and Synchronous Set 2-18

VHDL Code 2-19

Verilog Code 2-20

Flip-flop with Positive-Edge Clock and Clock Enable 2-20

VHDL Code 2-21

Verilog Code 2-22

4-bit Register with Positive-Edge Clock, Asynchronous Set and
��Clock Enable 2-22

Related Constraints 2-25

Latch with Positive Gate 2-26

Latch with Positive Gate and Asynchronous Clear 2-27

4-bit Latch with Inverted Gate and Asynchronous Preset 2-29

Related Constraints 2-31

Description Using Combinatorial Process and Always Block 2-32

VHDL Code 2-33

Verilog Code 2-33

Description Using Concurrent Assignment 2-34

4-bit Unsigned Up Counter with Asynchronous Clear 2-36

VHDL Code 2-36

Verilog Code 2-37

4-bit Unsigned Down Counter with Synchronous Set 2-38

VHDL Code 2-38

Verilog Code 2-39

4-bit Unsigned Up Counter with Asynchronous Load from Primary
��Input 2-39

VHDL Code 2-39

Verilog Code 2-40

4-bit Unsigned Up Counter with Synchronous Load with a
��Constant 2-41

VHDL Code 2-41

Verilog Code 2-42

4-bit Unsigned Up Counter with Asynchronous Clear and Clock
��Enable 2-42

VHDL Code 2-42

Verilog Code 2-43

4-bit Unsigned Up/Down counter with Asynchronous Clear 2-44

VHDL Code 2-44

Verilog Code 2-45

4-bit Signed Up Counter with Asynchronous Reset 2-45

4-bit Unsigned Up Accumulator with Asynchronous Clear 2-48

Related Constraints 2-53

8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and
��Serial Out 2-54

VHDL Code 2-54

Verilog Code 2-55

8-bit Shift-Left Register with Negative-Edge Clock, Clock Enable,
��Serial In, and Serial Out 2-55

VHDL Code 2-55

Verilog Code 2-56

8-bit Shift-Left Register with Positive-Edge Clock, Asynchronous
��Clear, Serial In, and Serial Out 2-57

VHDL Code 2-57

Verilog Code 2-58

8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Set, Serial In, and Serial Out 2-58

VHDL Code 2-59

Verilog Code 2-59

8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and
��Parallel Out 2-60

VHDL Code 2-61

Verilog Code 2-61

8-bit Shift-Left Register with Positive-Edge Clock, Asynchronous
��Parallel Load, Serial In, and Serial Out 2-62

VHDL Code 2-62

Verilog Code 2-63

8-bit Shift-Left Register with Positive-Edge Clock, Synchronous
��Parallel Load, Serial In, and Serial Out 2-63

VHDL Code 2-64

Verilog Code 2-65

8-bit Shift-Left/Shift-Right Register with Positive-Edge Clock, Serial
��In, and Parallel Out 2-65

Related Constraints 2-72

4-to-1 1-bit MUX using IF Statement 2-72

VHDL Code 2-72

Verilog Code 2-73

4-to-1 MUX Using CASE Statement 2-73

VHDL Code 2-73

Verilog Code 2-74

4-to-1 MUX Using Tristate Buffers 2-75

Related Constraints 2-78

VHDL (One-Hot) 2-78

Verilog (One-Hot) 2-79

VHDL (One-Cold) 2-80

Verilog (One-Cold) 2-81

Priority Encoders 2-86

Log File 2-86

3-Bit 1-of-9 Priority Encoder 2-86

Related Constraint 2-86

VHDL 2-87

Verilog 2-88

Logical Shifters 2-88

Log File 2-89

Related Constraints 2-89

Arithmetic Operations 2-94

Adders, Subtractors, Adders/Subtractors 2-95

Log File 2-95

Unsigned 8-bit Adder 2-96

Unsigned 8-bit Adder with Carry In 2-97

Unsigned 8-bit Adder with Carry Out 2-98

Unsigned 8-bit Adder with Carry In and Carry Out 2-100

Simple Signed 8-bit Adder 2-102

Unsigned 8-bit Subtractor 2-102

Unsigned 8-bit Adder/Subtractor 2-103

Comparators (=, /=,<, <=, >, >=) 2-105

Log File 2-105

Unsigned 8-bit Greater or Equal Comparator 2-105

Multipliers 2-106

Large Multipliers Using Block Multipliers 2-106

Registered Multiplier 2-107

Log File 2-108

Unsigned 8x4-bit Multiplier 2-108

Dividers 2-109

Log File 2-109

Division By Constant 2 2-110

Resource Sharing 2-111

Log File 2-112

Related Constraint 2-112

Example 2-112

RAMs 2-114

Log File 2-116

Related Constraints 2-117

Single-Port RAM with Asynchronous Read 2-117

VHDL 2-118

Verilog 2-119

Single-Port RAM with "false" Synchronous Read 2-120

Single-Port RAM with Synchronous Read (Read Through) 2-126

VHDL 2-127

Verilog 2-128

Single-Port RAM with Enable 2-129

VHDL 2-130

Verilog 2-131

Dual-Port RAM with Asynchronous Read 2-132

VHDL 2-133

Verilog 2-134

Dual-Port RAM with False Synchronous Read 2-135

VHDL 2-136

Verilog 2-137

Dual-Port RAM with Synchronous Read (Read Through) 2-138

Dual-Port RAM with One Enable Controlling Both Ports 2-144

VHDL 2-145

Verilog 2-146

Dual-Port RAM with Enable on Each Port 2-147

VHDL 2-148

Verilog 2-149

Multiple-Port RAM Descriptions 2-150

VHDL 2-151

Verilog 2-152

State Machines 2-152

Related Constraints 2-154

FSM with 1 Process 2-155

VHDL 2-155

Verilog 2-156

FSM with 2 Processes 2-157

VHDL 2-158

Verilog 2-159

FSM with 3 Processes 2-160

VHDL 2-160

Verilog 2-162

State Registers 2-163

Next State Equations 2-163

FSM Outputs 2-163

FSM Inputs 2-164

State Encoding Techniques 2-164

Black Box Support 2-167

Log File 2-167

Related Constraints 2-167

VHDL 2-168

Verilog 2-169

Chapter 3 FPGA Optimization

Introduction 3-1

Virtex Specific Synthesis Options 3-2

Timing Constraints 3-3

Domain Definitions 3-3

Supported Timing Constraints 3-5

Cross_Clock_Analysis: 3-10

Macro Generation 3-12

Arithmetic Functions 3-13

Loadable Functions 3-13

Multiplexers 3-14

Priority Encoder 3-14

Log File Analysis 3-18

Design Optimization 3-18

Implementation Constraints 3-23

Virtex Primitive Support 3-24

VHDL 3-26

Verilog 3-26

Log File 3-26

Instantiation of MUXF5 3-27

VHDL 3-27

Verilog 3-28

Instantiation of MUXF5 with XST Virtex Libraries 3-28

VHDL 3-28

Verilog 3-29

Related Constraints 3-29

Chapter 4 CPLD Optimization

CPLD Synthesis Options 4-1

Introduction 4-1

Global CPLD Synthesis Options 4-2

Families 4-2

List of Options 4-2

Implementation Details for Macro Generation 4-3

Log File Analysis 4-5

Constraints 4-6

Improving Results 4-7

How to Obtain Better Frequency? 4-8

How to Fit a Large Design? 4-9

Chapter 5 Design Constraints

Introduction 5-1

Setting Global Constraints and Options 5-2

Synthesis Options 5-3

HDL Options 5-6

Xilinx Specific Options 5-7

Command Line Options 5-9

VHDL Attribute Syntax 5-9

Verilog Meta Comment Syntax 5-10

Constraint File Syntax and Utilization 5-10

XST Constraints 5-11

HDL Inference and Optimization 5-14

FPGA Options 5-16

CPLD Options 5-21

Flip-Flop Retiming 5-22

Summary 5-23

Implementation Constraints 5-30

Third Party Constraints 5-32

Constraints Precedence 5-36

Chapter 6 VHDL Language Support

Introduction 6-2

Data Types in VHDL 6-2

Overloaded Data Types 6-4

Multi-dimensional Array Types 6-5

Record Types 6-6

Objects in VHDL 6-7

Operators 6-7

Entity and Architecture Descriptions 6-8

Entity Declaration 6-8

Architecture Declaration 6-8

Component Instantiation 6-9

Component Configuration 6-11

Generic Parameter Declaration 6-12

Combinatorial Circuits 6-13

Concurrent Signal Assignments 6-13

Simple Signal Assignment 6-13

Selected Signal Assignment 6-13

Conditional Signal Assignment 6-14

Generate Statement 6-15

Combinatorial Process 6-16

If...Else Statement 6-19

Case Statement 6-21

For...Loop Statement 6-22

Sequential Circuits 6-23

Sequential Process with a Sensitivity List 6-23

Sequential Process without a Sensitivity List 6-24

Examples of Register and Counter Descriptions 6-24

Multiple Wait Statements Descriptions 6-27

Functions and Procedures 6-29

Packages 6-32

STANDARD Package 6-32

IEEE Packages 6-33

Synopsys Packages 6-33

VHDL Language Support 6-34

VHDL Reserved Words 6-41

Chapter 7 Verilog Language Support

Introduction 7-2

Behavioral Verilog Features 7-3

Variable Declaration 7-3

Module Declaration 7-8

Verilog Assignments 7-9

Continuous Assignments 7-9

Procedural Assignments 7-10

Combinatorial always blocks 7-10

if...else statement 7-11

Case statement 7-11

For and Repeat loops 7-12

Sequential Always Blocks 7-14

Assign and Deassign Statements 7-16

Tasks and Functions 7-19

Blocking Versus Non-Blocking Procedural Assignments 7-22

Constants, Macros, Include Files and Comments 7-23

Structural Verilog Features 7-25

Parameters 7-28

Verilog Limitations in XST 7-29

Case Sensitivity 7-29

Blocking and Nonblocking Assignments 7-30

Integer Handling 7-31

Verilog Meta Comments 7-32

Language Support Tables 7-33

Primitives 7-37

Verilog Reserved Keywords 7-38

Chapter 8 Command Line Mode

Introduction 8-1

Launching XST 8-2

Setting Up an XST Script 8-3

Run Command 8-4

Set Command 8-8

Elaborate Command 8-9

Time Command 8-9

Example 1: How to Synthesize VHDL Designs Using Command Line
��Mode 8-10

Case 1: All Blocks in a Single File 8-10

XST Shell 8-11

Script Mode 8-12

Case 2: Each Design in a Separate File 8-13

Example 2: How to Synthesize Verilog Designs Using Command Line Mode 8-15

Case 1: All Design Blocks in a Single File 8-16

XST Shell 8-17

Script Mode 8-18

Case 2 8-19

Appendix A XST Naming Conventions

Net Naming Conventions A-1

Instance Naming Conventions A-2

alex9ufo 聰明人求知心切

2020年5月21日星期四