以Verilog 設計一個數位電路 (6)---3x8 decoder

  以Verilog 設計一個數位電路 (6)---3x8 decoder

module block1(
a,
b
);
input [2:0] a;
output [7:0] b;

wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_13;
wire SYNTHESIZED_WIRE_14;

assign SYNTHESIZED_WIRE_14 =  ~a[0];
assign SYNTHESIZED_WIRE_13 =  ~a[1];
assign SYNTHESIZED_WIRE_12 =  ~a[2];

assign b[0] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign b[1] = SYNTHESIZED_WIRE_12 & SYNTHESIZED_WIRE_13 & a[0];
assign b[2] = SYNTHESIZED_WIRE_12 & a[1] & SYNTHESIZED_WIRE_14;
assign b[3] = SYNTHESIZED_WIRE_12 & a[1] & a[0];
assign b[4] = a[2] & SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign b[5] = a[2] & SYNTHESIZED_WIRE_13 & a[0];
assign b[6] = a[2] & a[1] & SYNTHESIZED_WIRE_14;
assign b[7] = a[2] & a[1] & a[0];

endmodule

//==============================

`timescale 1 ns/1 ns

module EX_106 (a, b);

input [2:0] a;

output [7:0] b;

wire [7:0] b;

assign b[0] = ( a==3'b000 ) ? 1'b1 : 1'b0;

assign b[1] = ( a==3'b001 ) ? 1'b1 : 1'b0;

assign b[2] = ( a==3'b010 ) ? 1'b1 : 1'b0;

assign b[3] = ( a==3'b011 ) ? 1'b1 : 1'b0;

assign b[4] = ( a==3'b100 ) ? 1'b1 : 1'b0;

assign b[5] = ( a==3'b101 ) ? 1'b1 : 1'b0;

assign b[6] = ( a==3'b110 ) ? 1'b1 : 1'b0;

assign b[7] = ( a==3'b111 ) ? 1'b1 : 1'b0;

endmodule

//==============================

`timescale 100 ns/1 ns

module testbench;

reg [2:0] a;

wire[7:0] b;

integer i;

EX_106 UUT(

.a(a),

.b(b) );

initial

begin

 for (i=0;i<=7;i=i+1) begin

a=i;

  #20;

  end

  #20;

   $stop;

end

endmodule