Verilog code for NOR gate – All modeling styles

Verilog code for NOR gate – All modeling styles

Logic Circuit of the NOR gate

Gate Level modeling

module NOR_2_gate_level(output Y, input A, B);
   nor(Y, A, B); 
endmodule

Data flow modeling

module NOR_2_data_flow (output Y, input A, B);
assign Y = ~(A | B);
endmodule

Behavioral Modeling

Truth Table for NOR gate

A	B	Y(A nor B)
0	0	1
0	1	0
1	0	0
1	1	0

Equation from the truth table

Y = ~(A + B) or say Y = A nor B.

module NOR_2_behavioral (output reg Y, input A, B);
always @ (A or B) begin
    if (A == 1'b0 & B == 1'b0) begin
        Y = 1'b1;
    end
    else 
        Y = 1'b0; 
end
endmodule

RTL schematic of NOR gate

Testbench of the NOR gate using Verilog

`include "NOR_2_behavioral.v"

`timescale 100ns/1ns
module NOR_2_behavioral_tb;
reg A, B;
wire Y;
NOR_2_behavioral Instance0 (Y, A, B);
initial begin
    A = 0; B = 0;
 #1 A = 0; B = 1;
 #1 A = 1; B = 0;
 #1 A = 1; B = 1;   
end
initial begin
    $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
    $dumpfile("dump.vcd");
    $dumpvars();
end
endmodule

module NOR_2_behavioral (output reg Y, input A, B);
always @ (A or B) begin
    if (A == 1'b0 & B == 1'b0) begin
        Y = 1'b1;
    end
    else 
        Y = 1'b0; 
end
endmodule

//`include "NOR_2_behavioral.v"

`timescale 100ns/1ns

module NOR_2_behavioral_tb;

reg A, B;

wire Y;

NOR_2_behavioral UUT (Y, A, B);

initial begin

    A = 0; B = 0;

 #10 A = 0; B = 1;

 #10 A = 1; B = 0;

 #10 A = 1; B = 1;  

 #10 $stop;

  

end

initial begin

    $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);

    $dumpfile("dump.vcd");

    $dumpvars();

end

endmodule