以Verilog 設計一個數位電路 (9)---Parallel 4x1 MUX

以Verilog 設計一個數位電路 (9)---Parallel 4x1 MUX

`timescale 1 ns/1 ns

module EX_109 (a, b, c, d, sel, e);
input [7:0] a, b, c, d;
input [1:0] sel;
output [7:0] e;
wire [7:0] e;

assign e = (sel==2'b00) ? a :
            (sel==2'b01) ? b :
            (sel==2'b10) ? c : d;

endmodule

`timescale 100 ns/1 ns

module testbench;

reg [7:0] a, b, c, d;

reg [1:0] sel;

wire [7:0] e;

EX_109 UUT (

.a(a),

.b(b),

.c(c),

.d(d),

.sel(sel),

.e(e) );

initial

begin

 a   = 8'h00; // Time = 0

 b   = 8'h55;

 c   = 8'haa;

 d   = 8'hff;

 sel = 2'b00;

 #20; // Time = 20

 sel = 2'b01;

 #20; // Time = 40

 sel = 2'b10;

 #20; // Time = 60

 sel = 3'b11;

 #20;

 $stop;

 

end

endmodule