Verilog D Flip-Flop

Verilog D Flip-Flop 

module D_FF (clk,D,Q);
input clk,D;
output reg Q;
always@(posedge clk)
begin
Q=D;
end
endmodule

`timescale 100ns/1ns

module tb;

reg clk,D;

wire Q;

always #10 clk = ~clk;

D_FF UUT(clk,D,Q);

 initial begin

    // 1. Initialize testbench variables

clk=1'b0; D=1'b0;

   

    // 2. 

    repeat (2) @ (posedge clk);

    D <= 1;

    repeat (3) @ (posedge clk);

    // 3.  

    D <=0; 

    repeat(2) @ (posedge clk);

    D <= 1;

    // 4.  

    repeat (5) @ (posedge clk);

    $stop;

 

  end

endmodule