以Verilog 設計一個數位電路 (3)---and , not 邏輯閘

以Verilog 設計一個數位電路 (3)---and , not 邏輯閘

`timescale 1 ns/1 ns

module EX_103 (in1, in2, out1, out2);
input [3:0] in1, in2;
output [3:0] out1;
output out2;

wire [3:0]out1;
wire out2;

assign out1 = ~in1 & in2;
assign out2 = ~&in2;

endmodule

//=======================

// Test Bench

//=======================

`timescale 100ns/1 ns

module testbench;
reg [3:0]in1, in2;
wire [3:0]out1;
wire out2;
integer i;
EX_103 UUT(.in1(in1), .in2(in2), .out1(out1), .out2(out2) );
initial
begin
for (i=0;i<=3;i=i+1) begin
{in2[0],in1[0]}=i; {in2[1],in1[1]}=i;
{in2[2],in1[2]}=i; {in2[3],in1[3]}=i;

#20;

end

for (i=0;i<=15;i=i+1) begin
{in2}=i;

#20;
end
#20;
$stop;
end