以Verilog 設計一個數位電路 (4)---2x1MUX

以Verilog 設計一個數位電路 (4)---2x1MUX

`timescale 1 ns/1 ns

module EX_104 (a, b, c, sel);
input a, b, sel;
output c;
wire c;

assign c = ( sel == 1'b1 ) ? a : b;

endmodule

`timescale 100 ns/1 ns

module testbench;

reg a, b, sel;

wire c;

EX_104 UUT(

.a(a),

.b(b),

.c(c),

.sel(sel) );

integer i;

initial

begin

for (i=0;i<=7;i=i+1)begin

{sel,a,b}=i;

#20;

end

#20;

$stop;

end

endmodule